公开(公告)号：US20190196748A1

公开(公告)日：2019-06-27

申请号：US15850578

申请日：2017-12-21

Applicant: Microsoft Technology Licensing, LLC

Inventor： Anirudh BADAM ,  Badriddine KHESSIB ,  Laura Marie CAULFIELD ,  Mihail Gavril TARTA ,  Robin Andrew ALEXANDER ,  Xiaozhong XING ,  Zhe TAN ,  Jian XU

IPC: G06F3/06 ,  G06F9/54 ,  G06F9/455

CPC classification number: G06F3/0667 ,  G06F3/0605 ,  G06F3/0613 ,  G06F3/0631 ,  G06F3/064 ,  G06F3/0688 ,  G06F9/455 ,  G06F9/545 ,  G06F12/0246 ,  G06F2009/45587 ,  G06F2009/45595 ,  G06F2212/7201

Abstract: A system includes reception of a request from a first application to create a virtual open-channel solid state drive associated with a first bandwidth and first capacity, association, in response to the request, of block addresses of a virtual address space of the first application with block addresses of one or more blocks of a first one of a first plurality of channels of a first open-channel solid state drive and with block addresses of one or more blocks of a second one of a second plurality of channels of a second open-channel solid state drive, reception, from the first application, of a first I/O call associated with one or more block addresses of the virtual address space, determination of block addresses of one or more blocks of the first one of the first plurality of channels which are associated with the one or more block addresses of the virtual address space, and execution of the first I/O call on the determined block addresses of one or more blocks of the first one of the first plurality of channels.

公开(公告)号：US20190073478A1

公开(公告)日：2019-03-07

申请号：US15694748

申请日：2017-09-01

Applicant: Microsoft Technology Licensing, LLC

Inventor： Badriddine KHESSIB ,  Bryan David KELLY ,  Mallik BULUSU

IPC: G06F21/57 ,  G06F9/44 ,  G06F13/40 ,  G06F13/42

Abstract: A Root of Trust hardware hierarchy provides firmware security for motherboard and peripheral devices. Power is received at a computer system and, in response to the receipt of power, of a standby power rail of a motherboard of the computer system is energized, and a first microcontroller mounted on the motherboard authenticates first firmware associated with a baseboard management controller mounted on the motherboard and coupled to the first microcontroller. If the authentication of the first firmware is successful, the baseboard management controller is powered on, a central processing unit coupled to the first microcontroller is held in reset, and a standby power rail of a peripheral component card coupled to the motherboard is energized. Second firmware associated with the central processing unit is authenticated using the first microcontroller and a second microcontroller mounted on the peripheral component card authenticates third firmware associated with a system on chip mounted on the peripheral component card and coupled to the second microcontroller.

公开(公告)号：US20210311881A1

公开(公告)日：2021-10-07

申请号：US16910914

申请日：2020-06-24

Applicant: Microsoft Technology Licensing, LLC

Inventor： Badriddine KHESSIB

IPC: G06F12/1009 ,  G06F12/1027 ,  H03M7/30

Abstract: A memory management system includes a physical memory associated with a computing device and a memory manager. The memory manager is configured to manage a shared memory cache as part of a compression of the physical memory using a cache compression algorithm, wherein a compression block size for the compression is a single cache line size. The physical memory includes a sector translation table (STT) region and a sector memory region. The memory manager uses a memory descriptor defined by an STT entry having a cache line map and a plurality of sector pointers to load cache from the physical memory to a level 3 Cache. The cache line map contains cache line metadata including a size of each cache line, a location of the cache line in one of the sectors pointed to by the STT entry, and a plurality of flags.

公开(公告)号：US20190303047A1

公开(公告)日：2019-10-03

申请号：US16447094

申请日：2019-06-20

Applicant: Microsoft Technology Licensing, LLC

Inventor： Anirudh BADAM ,  Badriddine KHESSIB ,  Laura Marie CAULFIELD ,  Mihail Gavril TARTA ,  Robin Andrew ALEXANDER ,  Xiaozhong XING ,  Zhe TAN ,  Jian XU

IPC: G06F3/06 ,  G06F9/54 ,  G06F9/455 ,  G06F12/02

Abstract: A system includes reception of a request from a first application to create a virtual open-channel solid state drive associated with a first bandwidth and first capacity, association, in response to the request, of block addresses of a virtual address space of the first application with block addresses of one or more blocks of a first one of a first plurality of channels of a first open-channel solid state drive and with block addresses of one or more blocks of a second one of the first plurality of channels, reception, from the first application, of a first I/O call associated with one or more block addresses of the virtual address space, determination of block addresses of one or more blocks of the first one of the first plurality of channels which are associated with the one or more block addresses of the virtual address space, and execution of the first I/O call on the determined block addresses of one or more blocks of the first one of the first plurality of channels.