公开(公告)号：US20210055963A1

公开(公告)日：2021-02-25

申请号：US16591294

申请日：2019-10-02

Applicant: Microchip Technology Incorporated

Inventor： Hongming An ,  John Junling Zang ,  Henry Liang ,  Thor Xia ,  Congqing Xiong

IPC: G06F9/50 ,  G06F1/324 ,  H04L12/40 ,  G06F1/3209 ,  H04L12/10

Abstract: Circuitry for detecting valid signals on a single pair Ethernet bus and related systems are described. Also described are circuits and related systems for wake detection at a physical layer of a network segment, and in some embodiments, wake detection circuitry may include, or use, the signal detection circuitry. In some cases, a low frequency clock generator may be used to clock wake detection circuitry, including during low power modes of operation. In some cases, the low frequency clock generator may be enabled or disabled, selectively, to limit power consumption.