Write zero phase start for phase synchronization in bit patterned recording
    1.
    发明授权
    Write zero phase start for phase synchronization in bit patterned recording 有权
    在位图案记录中写入相位同步的零相位起始

    公开(公告)号:US08730605B1

    公开(公告)日:2014-05-20

    申请号:US13346941

    申请日:2012-01-10

    IPC分类号: G11B5/09 G11B5/596

    摘要: A bit patterned recording system includes a servo channel module configured to recover servo fields written with servo information. A field locator module is configured to locate a field printed to data islands of a medium based on a location of one of the servo fields. The servo islands and the data islands have different spacing. A servo clock has a different phase and frequency than a data clock. A phase error calculator module is configured to estimate a phase error of the data clock based on the field and the data clock. The phase error is used to adjust a phase of the data clock.

    摘要翻译: 有位图案记录系统包括:伺服信道模块,被配置为恢复用伺服信息写入的伺服字段。 场定位器模块被配置为基于伺服字段之一的位置来定位打印到介质的数据岛的字段。 伺服岛和数据岛具有不同的间距。 伺服时钟的相位和频率与数据时钟不同。 相位误差计算器模块被配置为基于场和数据时钟来估计数据时钟的相位误差。 相位误差用于调整数据时钟的相位。

    Bit-locked interface for magnetic recording
    2.
    发明授权
    Bit-locked interface for magnetic recording 失效
    用于磁记录的位锁接口

    公开(公告)号:US08693124B1

    公开(公告)日:2014-04-08

    申请号:US13172268

    申请日:2011-06-29

    IPC分类号: G11B5/09 G11B5/596

    CPC分类号: G11B5/59616 G11B5/09

    摘要: Techniques are provided for performing bit-locked operations on media. A first control signal is received from a first source, and a second control signal is generated at a second source in response to receiving the first control signal. The media is accessed according to the second control signal. One or more synchronization markers are located during the accessing of the media, and bit-level synchronization between the second source and the media is achieved based, at least partially, on the one or more synchronization markers. A control operation is performed on the media with bit-level synchrony between the second source and the media.

    摘要翻译: 提供了技术来执行媒体上的锁定操作。 响应于接收到第一控制信号,从第一源接收第一控制信号,并且在第二源产生第二控制信号。 根据第二控制信号来访问介质。 在媒体访问期间定位一个或多个同步标记,并且至少部分地基于一个或多个同步标记来实现第二源和介质之间的位级同步。 在第二个源和媒体之间的位级同步的介质上执行控制操作。

    Disk synchronous write architecture for bit-patterned recording
    3.
    发明授权
    Disk synchronous write architecture for bit-patterned recording 有权
    用于位图记录的磁盘同步写架构

    公开(公告)号:US08879185B1

    公开(公告)日:2014-11-04

    申请号:US13288276

    申请日:2011-11-03

    IPC分类号: G11B5/09

    CPC分类号: G11B5/746 G11B5/59616

    摘要: Systems, methods, apparatus, and techniques are provided for controlling synchronization of a write clock. A frequency offset is estimated based, at least partially, on a location of the servo synchronization marker to produce the frequency offset estimate. A phase correction value and a frequency correction value associated with the write clock are obtained, and a data clock timing control signal is produced based on the frequency offset estimate, the phase correction value, and the frequency correction value. The data clock timing control signal is applied to a phase interpolator to modify a phase of the write clock.

    摘要翻译: 提供了用于控制写时钟的同步的系统,方法,装置和技术。 至少部分地基于伺服同步标记的位置来估计频率偏移,以产生频率偏移估计。 获得与写时钟相关联的相位校正值和频率校正值,并且基于频率偏移估计,相位校正值和频率校正值产生数据时钟定时控制信号。 数据时钟定时控制信号被施加到相位插值器以修改写入时钟的相位。

    Systems and methods for gain compensation and re-timing in magnetic recording channels
    4.
    发明授权
    Systems and methods for gain compensation and re-timing in magnetic recording channels 有权
    磁记录通道增益补偿和重新定时的系统和方法

    公开(公告)号:US08649120B1

    公开(公告)日:2014-02-11

    申请号:US13365658

    申请日:2012-02-03

    IPC分类号: G11B5/09 G11B5/035

    摘要: A receiver for a hard disk drive system includes an analog front end module configured to receive a read-back signal and to output a digital read-back signal. An equalizer module is configured to generate a data vector based on the digital read-back signal. A detector module is configured to generate a decision vector based on the data vector. A gain module is configured to generate a scalar gain vector and to generate a revised data vector based on the data vector, the decision vector and the scalar gain vector. A back end module is configured to receive the revised data vector.

    摘要翻译: 用于硬盘驱动器系统的接收器包括被配置为接收回读信号并输出​​数字回读信号的模拟前端模块。 均衡器模块被配置为基于数字回读信号生成数据向量。 检测器模块被配置为基于数据向量生成决策向量。 增益模块被配置为生成标量增益矢量并且基于所述数据矢量,所述决策向量和所述标量增益矢量来生成修正数据矢量。 后端模块被配置为接收修改的数据向量。

    Timing acquisition robust to inter-track-interference
    5.
    发明授权
    Timing acquisition robust to inter-track-interference 有权
    定时采集对于轨道间干扰是稳健的

    公开(公告)号:US08693118B1

    公开(公告)日:2014-04-08

    申请号:US13551016

    申请日:2012-07-17

    IPC分类号: G11B5/02

    摘要: A system includes a preamble determination module configured to determine an expected preamble of a target track. The expected preamble includes an associated timing recovery pattern. A filter module is configured to receive a readback signal read from the target track based on the expected preamble, and selectively filter the readback signal to remove inter track interference from the readback signal based on the expected preamble.

    摘要翻译: 系统包括被配置为确定目标轨道的预期前导码的前导码确定模块。 期望的前导码包括相关的定时恢复模式。 滤波器模块被配置为基于预期的前导码接收从目标轨道读取的回读信号,并且基于预期的前导码选择性地过滤回读信号以从回读信号中去除干扰。

    Methods and apparatus for performing interpolated timing recovery
    6.
    发明授权
    Methods and apparatus for performing interpolated timing recovery 有权
    用于执行内插定时恢复的方法和装置

    公开(公告)号:US08395858B1

    公开(公告)日:2013-03-12

    申请号:US13285772

    申请日:2011-10-31

    IPC分类号: G11B5/09 G11B5/035

    摘要: Methods and apparatus are provided for performing interpolated timing recovery using a frequency and phase estimate. An analog signal representing a sector is asynchronously sampled and stored in a storage device. A retiming circuit reads the stored samples and, based on first portions of first and second timing portions of the sector, determines phase adjustments. The retiming circuit generates a signal representing the samples at the adjusted phase and determines sample shift adjustments based on the generated signal and second portions of the first and second timing portions. The retiming circuit computes start and end indices of the sector in the buffer based on the sample shift adjustment and phase adjustment. The start and end indices may be used to compute a frequency estimate. The frequency estimate and a phase adjustment is used to interpolate the asynchronous samples at the appropriate frequency and phase.

    摘要翻译: 提供了使用频率和相位估计来执行内插定时恢复的方法和装置。 表示扇区的模拟信号被异步采样并存储在存储设备中。 重新定时电路读取存储的采样,并且基于扇区的第一和第二定时部分的第一部分来确定相位调整。 重新定时电路产生表示在调整阶段的采样的信号,并且基于产生的信号和第一和第二定时部分的第二部分来确定采样位移调整。 重新定时电路基于样本移位调整和相位调整来计算缓冲器中扇区的起始和终止索引。 开始和结束索引可用于计算频率估计。 频率估计和相位调整用于在适当的频率和相位内插异步采样。

    Methods and apparatus for performing interpolated timing recovery
    7.
    发明授权
    Methods and apparatus for performing interpolated timing recovery 有权
    用于执行内插定时恢复的方法和装置

    公开(公告)号:US08049983B1

    公开(公告)日:2011-11-01

    申请号:US12323247

    申请日:2008-11-25

    IPC分类号: G11B5/09 G11B5/035

    摘要: Methods and apparatus are provided for performing interpolated timing recovery using a frequency and phase estimate. An analog signal representing a sector is asynchronously sampled and stored in a storage device. A retiming circuit reads the stored samples and, based on first portions of first and second timing portions of the sector, determines phase adjustments. The retiming circuit generates a signal representing the samples at the adjusted phase and determines sample shift adjustments based on the generated signal and second portions of the first and second timing portions. The retiming circuit computes start and end indices of the sector in the buffer based on the sample shift adjustment and phase adjustment. The start and end indices may be used to compute a frequency estimate. The frequency estimate and a phase adjustment is used to interpolate the asynchronous samples at the appropriate frequency and phase.

    摘要翻译: 提供了使用频率和相位估计来执行内插定时恢复的方法和装置。 表示扇区的模拟信号被异步采样并存储在存储设备中。 重新定时电路读取存储的采样,并且基于扇区的第一和第二定时部分的第一部分来确定相位调整。 重新定时电路产生表示在调整阶段的采样的信号,并且基于产生的信号和第一和第二定时部分的第二部分来确定采样位移调整。 重新定时电路基于样本移位调整和相位调整来计算缓冲器中扇区的起始和终止索引。 开始和结束索引可用于计算频率估计。 频率估计和相位调整用于在适当的频率和相位内插异步采样。

    Systems and methods for inter-track interference cancellation in magnetic recording channels
    8.
    发明授权
    Systems and methods for inter-track interference cancellation in magnetic recording channels 有权
    磁记录通道中轨道间干扰消除的系统和方法

    公开(公告)号:US08537482B1

    公开(公告)日:2013-09-17

    申请号:US13365696

    申请日:2012-02-03

    IPC分类号: G11B5/09 G11B5/035

    摘要: A receiver for a hard disk drive system includes an analog front end module configured to sample a read-back signal and to output a digital read-back signal. An equalizer module is configured to generate a data vector based on the digital read-back signal. A detector module is configured to generate a decision vector based on the data vector. A re-timing module is configured to generate a first revised data vector based on the data vector and the decision vector. The re-timing module re-samples a plurality of samples in the data vector in a non-sequential time order to generate the first revised data vector. An inter-track interference (ITI) cancellation module is configured to remove ITI from the first revised data vector and to generate a second revised data vector.

    摘要翻译: 用于硬盘驱动器系统的接收器包括被配置为对回读信号进行采样并输出数字回读信号的模拟前端模块。 均衡器模块被配置为基于数字回读信号生成数据向量。 检测器模块被配置为基于数据向量生成决策向量。 重新定时模块被配置为基于数据向量和决策向量生成第一修订数据向量。 重新定时模块以非连续时间顺序重新采样数据向量中的多个样本,以生成第一修订数据向量。 轨道间干扰(ITI)消除模块被配置为从第一修订数据向量中移除ITI并生成第二修订数据向量。

    Harmonic sensor
    9.
    发明授权
    Harmonic sensor 有权
    谐波传感器

    公开(公告)号:US08422160B1

    公开(公告)日:2013-04-16

    申请号:US13442033

    申请日:2012-04-09

    IPC分类号: G11B5/60

    摘要: A system includes an input circuit, an analog to digital converter, first and second harmonic sensor modules, a head height control module, and a weighting function module. The input circuit receives analog signals from a read/write head. The analog to digital converter generates digital samples in response to the analog signals. The first and second harmonic sensor modules determine, from the digital samples, a first magnitude of a first frequency component and a second magnitude of a second frequency component, respectively. The head height control module estimates a height of the head over a storage medium in response to a comparison of the first magnitude and the second magnitude, and selectively adjusts the height in response to the estimated height. The weighting function module applies a time domain window function to the digital samples to create modified samples on which the first and second harmonic sensor modules operate.

    摘要翻译: 系统包括输入电路,模数转换器,第一和第二谐波传感器模块,磁头高度控制模块和加权功能模块。 输入电路从读/写头接收模拟信号。 模数转换器响应于模拟信号产生数字采样。 第一和第二谐波传感器模块分别从数字样本确定第一频率分量的第一幅度和第二频率分量的第二幅度。 头部高度控制模块响应于第一幅度和第二幅度的比较来估计头部在存储介质上的高度,并且响应于估计的高度选择性地调整高度。 加权功能模块将时域窗函数应用于数字样本,以创建第一和第二谐波传感器模块所在的修改样本。

    Analog techniques to decode signals extracted from computer-readable storage media
    10.
    发明授权
    Analog techniques to decode signals extracted from computer-readable storage media 有权
    用于解码从计算机可读存储介质提取的信号的模拟技术

    公开(公告)号:US08405928B1

    公开(公告)日:2013-03-26

    申请号:US13353193

    申请日:2012-01-18

    IPC分类号: G11B5/596

    CPC分类号: G11B5/59627

    摘要: Methods, apparatuses, and systems implementing analog techniques to decode signals extracted from servo wedges of computer-readable storage media. A digital representation of at least a portion of a repeatable runout (RRO) signal derived from an analog signal read from a computer-readable storage medium is obtained. An estimate of a magnitude of the RRO signal is determined based on the digital representation. An error signal is generated to represent a difference between the estimate of the magnitude and a specified level of the magnitude of the RRO signal, and a gain value is configured, based on the error signal, for decoding a signal from the computer-readable storage medium.

    摘要翻译: 实现模拟技术以解码从计算机可读存储介质的伺服楔中提取的信号的方法,装置和系统。 获得从从计算机可读存储介质读取的模拟信号导出的可重复跳动(RRO)信号的至少一部分的数字表示。 基于数字表示来确定RRO信号的幅度的估计。 产生误差信号以表示幅度的估计与RRO信号的规定电平之间的差异,并且基于误差信号配置增益值,用于对来自计算机可读存储器的信号进行解码 中。