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1.发明授权Method and system for transmitting or receiving N-bit video data over a serial link 有权用于通过串行链路发送或接收N位视频数据的方法和系统公开(公告)号：US08311126B2
公开(公告)日：2012-11-13
申请号：US12501637
申请日：2009-07-13
IPC分类号： H04N7/18
CPC分类号： G06F3/14 , G09G3/2092 , G09G5/006
摘要： A system including a receiver, a TMDS link (or other serial link), and a transmitter configured to transmit K-bit video words (typically, encoded 8-bit video words) over the link. In typical embodiments, the transmitter is configured to pack a sequence of N-bit video words, where N≠K (e.g., N=10, 12, or 16, when K=8) into a sequence of K-bit fragments, encode the fragments, and transmit the encoded fragments. The transmitted data are indicative of a sequence of M-fragment groups, and the transmitter is typically configured also to transmit over the link packing phase data indicative of the phase of the most recently transmitted fragment. Other aspects are transmitters and receivers for use in such a system and methods implemented by any such transmitter, receiver, or system.
摘要翻译： 包括接收机，TMDS链路（或其他串行链路）的系统和被配置为通过链路发送K位视频字（通常是编码的8位视频字）的发射机。 在典型实施例中，发射机被配置为将N≠K（例如，当K = 8时N = 10,12或16）N位视频字序列打包成K位片段序列， 片段，并传输编码片段。 发送的数据指示M个片段组的序列，并且发射机通常也被配置为也通过链路打包相位发送指示最近发送的片段的相位的数据。 其他方面是用于这种系统的发射机和接收机以及由任何这样的发射机，接收机或系统实现的方法。
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2.发明申请Method and System for Transmitting or Receiving N-Bit Video Data over a Serial Link 有权通过串行链路发送或接收N位视频数据的方法和系统公开(公告)号：US20090274218A1
公开(公告)日：2009-11-05
申请号：US12501637
申请日：2009-07-13
IPC分类号： H04L27/00
CPC分类号： G06F3/14 , G09G3/2092 , G09G5/006
摘要： A system including a receiver, a TMDS link (or other serial link), and a transmitter configured to transmit K-bit video words (typically, encoded 8-bit video words) over the link. In typical embodiments, the transmitter is configured to pack a sequence of N-bit video words, where N≠K (e.g., N=10, 12, or 16, when K=8) into a sequence of K-bit fragments, encode the fragments, and transmit the encoded fragments. The transmitted data are indicative of a sequence of M-fragment groups, and the transmitter is typically configured also to transmit over the link packing phase data indicative of the phase of the most recently transmitted fragment. Other aspects are transmitters and receivers for use in such a system and methods implemented by any such transmitter, receiver, or system.
摘要翻译： 包括接收机，TMDS链路（或其他串行链路）的系统和被配置为通过链路发送K位视频字（通常是编码的8位视频字）的发射机。 在典型的实施例中，发射机被配置为将N个比特视频字序列进行打包，其中NK（例如，当K = 8时N = 10,12或16）到K比特片段的序列中， ，并传送编码片段。 发送的数据指示M个片段组的序列，并且发射机通常也被配置为也通过链路打包相位发送指示最近发送的片段的相位的数据。 其他方面是用于这种系统的发射机和接收机以及由任何这样的发射机，接收机或系统实现的方法。
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3.发明授权公开(公告)号：US07599439B2
公开(公告)日：2009-10-06
申请号：US11166458
申请日：2005-06-24
IPC分类号： H04N7/18
CPC分类号： G06F3/14 , G09G3/2092 , G09G5/006
摘要： A system including a receiver, a TMDS link (or other serial link), and a transmitter configured to transmit K-bit video words (typically, encoded 8-bit video words) over the link. In typical embodiments, the transmitter is configured to pack a sequence of N-bit video words, where N≠K (e.g., N=10, 12, or 16, when K=8) into a sequence of K-bit fragments, encode the fragments, and transmit the encoded fragments. The transmitted data are indicative of a sequence of M-fragment groups, and the transmitter is typically configured also to transmit over the link packing phase data indicative of the phase of the most recently transmitted fragment. Other aspects are transmitters and receivers for use in such a system and methods implemented by any such transmitter, receiver, or system.
摘要翻译： 包括接收机，TMDS链路（或其他串行链路）的系统和被配置为通过链路发送K位视频字（通常为编码的8位视频字）的发射机。 在典型的实施例中，发射机被配置为将N个比特视频字序列打包到一个K比特片段序列中，其中N
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公开(公告)号：US07027064B2
公开(公告)日：2006-04-11
申请号：US10086174
申请日：2002-02-28
CPC分类号： G09G5/39 , G06F12/0804 , G06F12/0897 , G06F12/126 , G06F2212/455 , G06T1/60 , G09G2360/121
摘要： An external cache management unit for use with 3D-RAM and suitable for use in a computer graphics system is described. The unit maintains and tracks the status of level one cache memory in the 3D-RAM. The unit identifies dirty blocks of cache memory and prioritizes block cleansing based on a least used algorithm. Periodic block cleansing during empty memory cycles is provided for, and may also be prompted on demand.
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公开(公告)号：US06847369B2
公开(公告)日：2005-01-25
申请号：US10060915
申请日：2002-01-30
摘要： A data queue optimized for receiving loosely packed graphics data and suitable for use in a computer graphics system is described. The data queue operates on first-in-first-out principals, and has a variable width input and output. The variable width on the input side facilitates the reception and storage of loosely packed data. The variable width output allows for the single-cycle output of multi-word data. Packing of the data occurs on the write-side of the FIFO structure.
摘要翻译： 描述了优化用于接收松散封装的图形数据并适合于在计算机图形系统中使用的数据队列。 数据队列以先进先出原则进行操作，并具有可变宽度的输入和输出。 输入侧的可变宽度有助于松散打包数据的接收和存储。 可变宽度输出允许多字数据的单周期输出。 数据的包装发生在FIFO结构的写入端。
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6.发明授权System and method for performing font operations when background color is transparent 有权当背景颜色透明时执行字体操作的系统和方法公开(公告)号：US06831645B2
公开(公告)日：2004-12-14
申请号：US10092378
申请日：2002-03-05
IPC分类号： G06T1100
CPC分类号： G06T15/503 , G06T11/203 , G06T11/40
摘要： One embodiment of a method of performing a font operation involves receiving a set of font data identifying a font operation to be performed. If a first font data unit in the set indicates that a first coordinate should be a background color and transparent background is enabled, the method involves outputting an enable for a second font data unit in the set. The second font data unit indicates that a second coordinate should be a foreground color. The enable for the second coordinate is output instead of a disable for the first coordinate. If instead the first font data unit in the set indicates that the first coordinate should be a background color and transparent background is disabled, the method may involve outputting a disable for the first coordinate.
摘要翻译： 执行字体操作的方法的一个实施例涉及接收识别要执行的字体操作的一组字体数据。 如果集合中的第一字体数据单元指示第一坐标应该是背景颜色并且透明背景被使能，则该方法涉及输出集合中的第二字体数据单元的使能。 第二字体数据单元指示第二坐标应为前景色。 输出第二个坐标的启用而不是第一个坐标的禁用。 如果相反，集合中的第一字体数据单元指示第一坐标应该是背景颜色，并且透明背景被禁用，则该方法可以涉及输出用于第一坐标的禁用。
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公开(公告)号：US06784894B2
公开(公告)日：2004-08-31
申请号：US09861176
申请日：2001-05-18
IPC分类号： G06T1500
CPC分类号： G09G5/363 , G06T15/005 , G09G5/393 , G09G5/395
摘要： A graphics system configured to operate on a collection of vertices to determine mappings from an initial order to secondary and tertiary ordering. The initial order corresponds to the ordering of the vertices in an input buffer. The secondary (tertiary) ordering corresponds to the ordering of the vertices along a triangle major (minor) axis. The graphics system computes horizontal and vertical displacements along edges of the triangle in the initial ordering, and uses the signs of the horizontal displacements and vertical displacements to access a mapping table which determines the mappings. The mappings may be used to rasterize the triangle in terms of pixels (or samples).
摘要翻译： 图形系统被配置为对顶点集合进行操作以确定从初始顺序到二次和三次排序的映射。 初始顺序对应于输入缓冲区中顶点的顺序。 次级（三级）排序对应于沿着三角形主（次）轴的顶点的顺序。 图形系统在初始排序中计算沿着三角形边缘的水平和垂直位移，并使用水平位移和垂直位移的符号来访问确定映射的映射表。 映射可以用于根据像素（或样本）来对三角形进行光栅化。
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8.发明授权Graphics system having a super-sampled sample buffer and having single sample per pixel support 有权图形系统具有超采样采样缓冲器并且每像素支持单个采样公开(公告)号：US06650323B2
公开(公告)日：2003-11-18
申请号：US10194976
申请日：2002-07-12
申请人： Nathaniel David Naegle , Michael F. Deering , Michael G. Lavelle , Carol A. Lavelle , Scott R. Nelson
发明人： Nathaniel David Naegle , Michael F. Deering , Michael G. Lavelle , Carol A. Lavelle , Scott R. Nelson
IPC分类号： G06T1500
CPC分类号： G09G5/391 , G06T15/503 , G09G5/14 , G09G5/363 , G09G5/397 , G09G2340/0407 , G09G2354/00 , G09G2360/10 , G09G2360/121
摘要： A computer graphics system that utilizes a super-sampled sample buffer and a sample-to-pixel calculation unit for refreshing the display. The graphics system may have a graphics processor, a super-sampled sample buffer, and a sample-to-pixel calculation unit. The graphics processor renders samples into the sample buffer and may utilize a window ID that specifies attributes of pixels on a per object basis. The window ID may specify one or more of a sample mode, filter type, color attributes, or source attributes. The sample mode may include single sample per pixel mode and multiple samples per pixel mode. The graphics system may be further operable to generate a single sample per pixel for certain windows of the screen in order to provide backwards compatibility with legacy systems.
摘要翻译： 利用超采样采样缓冲器和用于刷新显示器的采样到像素计算单元的计算机图形系统。 图形系统可以具有图形处理器，超采样采样缓冲器和采样到像素的计算单元。 图形处理器将样本呈现到样本缓冲器中，并且可以利用在每个对象的基础上指定像素的属性的窗口ID。 窗口ID可以指定样本模式，过滤器类型，颜色属性或源属性中的一个或多个。 样本模式可以包括每像素模式的单个样本和每像素模式的多个采样。 图形系统可以进一步可操作以为屏幕的某些窗口生成每个像素的单个样本，以便向遗留系统提供向后兼容性。
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公开(公告)号：US06262748B1
公开(公告)日：2001-07-17
申请号：US08966546
申请日：1997-11-10
IPC分类号： G06F1314
CPC分类号： G09G5/39 , G06T15/005 , G09G5/399 , G09G2340/10 , G09G2360/121 , G09G2360/123 , G09G2360/126
摘要： A frame buffer dynamic random access memory (FBRAM) is disclosed that enables accelerated rendering of Z-buffered graphics primitives. The FBRAM converts read-modify-write transactions such as Z-buffer compare and RBG alpha blending into a write only operation. The FBRAM also implements two levels of internal pixel caches, and a four-way interleaved frame buffer.
摘要翻译： 公开了一种帧缓冲器动态随机存取存储器（FBRAM），其实现了Z缓冲图形基元的加速渲染。 FBRAM将读取 - 修改 - 写入事务（如Z缓冲区比较和RBG alpha混合）转换为只写操作。 FBRAM还实现了两级内部像素高速缓存和四路交错帧缓冲器。
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公开(公告)号：US20110221742A1
公开(公告)日：2011-09-15
申请号：US12898249
申请日：2010-10-05
IPC分类号： G06T15/00
CPC分类号： G06T1/20 , G06T1/60 , G06T5/002 , G06T15/005
摘要： A high-speed ring topology. In one embodiment, two base chip types are required: a “drawing” chip, LoopDraw, and an “interface” chip, LoopInterface. Each of these chips have a set of pins that supports an identical high speed point to point unidirectional input and output ring interconnect interface: the LoopLink. The LoopDraw chip uses additional pins to connect to several standard memories that form a high bandwidth local memory sub-system. The LoopInterface chip uses additional pins to support a high speed host computer host interface, at least one video output interface, and possibly also additional non-local interconnects to other LoopInterface chip(s).
摘要翻译： 高速环形拓扑。 在一个实施例中，需要两种基本芯片类型：“绘图”芯片，LoopDraw和“接口”芯片，LoopInterface。 每个芯片都有一组引脚，支持相同的高速点对点输入和输出环互连接口：LoopLink。 LoopDraw芯片使用额外的引脚连接到形成高带宽本地存储器子系统的多个标准存储器。 LoopInterface芯片使用额外的引脚来支持高速主机主机接口，至少一个视频输出接口，以及可能与其他LoopInterface芯片的附加非本地互连。
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