公开(公告)号：US20110241915A1

公开(公告)日：2011-10-06

申请号：US13159856

申请日：2011-06-14

Applicant: Yu-Jen Lai ,  Mei-Chen Chuang ,  Wen-Shen Chou

Inventor： Yu-Jen Lai ,  Mei-Chen Chuang ,  Wen-Shen Chou

IPC: H03M1/10

CPC classification number: H03M1/1061 ,  H03M1/687 ,  H03M1/745 ,  H03M1/747

Abstract: A system and method for converting a digital signal to an analog signal is provided. The present disclosure provides a digital-to-analog converter (DAC) that can convert a large bit value digital signal to a corresponding analog signal. In accordance with an embodiment, a method comprises receiving portions of a digital signal by a plurality of sub-DACs; converting the portions of the digital signal to a corresponding analog signal by the plurality of sub-DACs; biasing one or more of the plurality of sub-DACs; and calibrating the portions of a digital signal by one or more calibration elements.

Abstract translation: 提供了一种将数字信号转换为模拟信号的系统和方法。 本公开提供了一种数模转换器（DAC），其可以将大位值数字信号转换为对应的模拟信号。 根据实施例，一种方法包括：通过多个子DAC接收数字信号的部分; 通过所述多个子DAC将所述数字信号的所述部分转换成相应的模拟信号; 偏置所述多个子DAC中的一个或多个; 以及通过一个或多个校准元件校准数字信号的部分。

公开(公告)号：US07852250B2

公开(公告)日：2010-12-14

申请号：US12340462

申请日：2008-12-19

Applicant: Mei-Chen Chuang ,  Wen-Shen Chou

Inventor： Mei-Chen Chuang ,  Wen-Shen Chou

IPC: H03M1/66

CPC classification number: H03M1/687 ,  H03M1/745 ,  H03M1/747

Abstract: This invention discloses a digital to analog converter (DAC) for converting a digital signal with a predetermined number of bits to a corresponding analog signal, the DAC comprises a first current source element having a first control signal, the first control signal controlling the conduction current provided by the first current source element, and a second current source element having a second control signal, the second control signal controlling the conduction current provided by the second current source element, wherein the first and the second control signals have different voltages during operation of the DAC.

Abstract translation: 本发明公开了一种用于将预定位数的数字信号转换为相应模拟信号的数模转换器（DAC），该DAC包括具有第一控制信号的第一电流源元件，第一控制信号控制导通电流 由第一电流源元件提供，以及具有第二控制信号的第二电流源元件，所述第二控制信号控制由第二电流源元件提供的传导电流，其中第一和第二控制信号在运行期间具有不同的电压 DAC。

公开(公告)号：US20100283642A1

公开(公告)日：2010-11-11

申请号：US12708417

申请日：2010-02-18

Applicant: Yu-Jen Lai ,  Mei-Chen Chuang ,  Wen-Shen Chou

Inventor： Yu-Jen Lai ,  Mei-Chen Chuang ,  Wen-Shen Chou

IPC: H03M1/10 ,  H03M1/66

CPC classification number: H03M1/1061 ,  H03M1/687 ,  H03M1/745 ,  H03M1/747

Abstract: A system for converting a digital signal to an analog signal is provided. The present invention provides a digital-to-analog converter (DAC) that can convert a large bit value digital signal to a corresponding analog signal. The digital-to-analog converter includes a bias regeneration circuit, and three sub-DACs. The bias regeneration circuit provides biasing to the three sub-DACs allowing the DAC to be implemented with smaller circuit area. In addition, the three sub-DACs may be digitally calibrated during the conversion process to increase the linearity of the DAC.

Abstract translation: 提供了一种将数字信号转换为模拟信号的系统。 本发明提供一种数模转换器（DAC），其可以将大比特数字数字信号转换成对应的模拟信号。 数模转换器包括偏置再生电路和三个子DAC。 偏置再生电路为三个子DAC提供偏置，允许以较小的电路面积实现DAC。 此外，三个子DAC可以在转换过程中进行数字校准，以增加DAC的线性度。

公开(公告)号：US08599057B2

公开(公告)日：2013-12-03

申请号：US13159856

申请日：2011-06-14

Applicant: Yu-Jen Lai ,  Mei-Chen Chuang ,  Wen-Shen Chou

Inventor： Yu-Jen Lai ,  Mei-Chen Chuang ,  Wen-Shen Chou

IPC: H03M1/66

CPC classification number: H03M1/1061 ,  H03M1/687 ,  H03M1/745 ,  H03M1/747

Abstract: A system and method for converting a digital signal to an analog signal is provided. The present disclosure provides a digital-to-analog converter (DAC) that can convert a large bit value digital signal to a corresponding analog signal. In accordance with an embodiment, a method comprises receiving portions of a digital signal by a plurality of sub-DACs; converting the portions of the digital signal to a corresponding analog signal by the plurality of sub-DACs; biasing one or more of the plurality of sub-DACs; and calibrating the portions of a digital signal by one or more calibration elements.

Abstract translation: 提供了一种将数字信号转换为模拟信号的系统和方法。 本公开提供了一种数模转换器（DAC），其可以将大位值数字信号转换为对应的模拟信号。 根据实施例，一种方法包括：通过多个子DAC接收数字信号的部分; 通过所述多个子DAC将所述数字信号的所述部分转换成相应的模拟信号; 偏置所述多个子DAC中的一个或多个; 以及通过一个或多个校准元件校准数字信号的部分。

公开(公告)号：US07978110B2

公开(公告)日：2011-07-12

申请号：US12708417

申请日：2010-02-18

Applicant: Yu-Jen Lai ,  Mei-Chen Chuang ,  Wen-Shen Chou

Inventor： Yu-Jen Lai ,  Mei-Chen Chuang ,  Wen-Shen Chou

IPC: H03M1/66

CPC classification number: H03M1/1061 ,  H03M1/687 ,  H03M1/745 ,  H03M1/747

Abstract: A system for converting a digital signal to an analog signal is provided. The present invention provides a digital-to-analog converter (DAC) that can convert a large bit value digital signal to a corresponding analog signal. The digital-to-analog converter includes a bias regeneration circuit, and three sub-DACs. The bias regeneration circuit provides biasing to the three sub-DACs allowing the DAC to be implemented with smaller circuit area. In addition, the three sub-DACs may be digitally calibrated during the conversion process to increase the linearity of the DAC.

Abstract translation: 提供了一种将数字信号转换为模拟信号的系统。 本发明提供一种数模转换器（DAC），其可以将大比特数字数字信号转换成对应的模拟信号。 数模转换器包括偏置再生电路和三个子DAC。 偏置再生电路为三个子DAC提供偏置，允许以较小的电路面积实现DAC。 此外，三个子DAC可以在转换过程中进行数字校准，以增加DAC的线性度。

公开(公告)号：US20090278723A1

公开(公告)日：2009-11-12

申请号：US12340462

申请日：2008-12-19

Applicant: Mei-Chen Chuang ,  Wen-Shen Chou

Inventor： Mei-Chen Chuang ,  Wen-Shen Chou

IPC: H03M1/66

CPC classification number: H03M1/687 ,  H03M1/745 ,  H03M1/747

Abstract: This invention discloses a digital to analog converter (DAC) for converting a digital signal with a predetermined number of bits to a corresponding analog signal, the DAC comprises a first current source element having a first control signal, the first control signal controlling the conduction current provided by the first current source element, and a second current source element having a second control signal, the second control signal controlling the conduction current provided by the second current source element, wherein the first and the second control signals have different voltages during operation of the DAC.

Abstract translation: 本发明公开了一种用于将预定位数的数字信号转换为相应模拟信号的数模转换器（DAC），该DAC包括具有第一控制信号的第一电流源元件，第一控制信号控制导通电流 由第一电流源元件提供，以及具有第二控制信号的第二电流源元件，所述第二控制信号控制由第二电流源元件提供的传导电流，其中第一和第二控制信号在运行期间具有不同的电压 DAC。

公开(公告)号：US08587368B2

公开(公告)日：2013-11-19

申请号：US13460432

申请日：2012-04-30

Applicant: Chi-Ping Yao ,  Wen-Shen Chou

Inventor： Chi-Ping Yao ,  Wen-Shen Chou

IPC: G05F1/10

CPC classification number: G05F3/30

Abstract: A method includes generating a first current, wherein the first current flows through a first resistor and a first bipolar transistor. A first end of the first resistor is serially connected to an emitter-collector path of the first bipolar transistor, and a second end of the resistor is connected to an input of an operational amplifier. A second current is generated to flow through a second resistor that is connected to the input of the operational amplifier. An emitter of a second bipolar transistor is connected to a base of the first bipolar transistor, wherein a base and a collector of the second bipolar transistor are connected to VSS. The first and the second currents are added to generate a third current, which is mirrored to generate a fourth current proportional to the third current. The fourth current is conducted through a third resistor to generate an output reference voltage.

Abstract translation: 一种方法包括产生第一电流，其中第一电流流过第一电阻器和第一双极晶体管。 第一电阻器的第一端串联连接到第一双极晶体管的发射极 - 集电极路径，并且电阻器的第二端连接到运算放大器的输入端。 产生第二电流以流过连接到运算放大器的输入端的第二电阻器。 第二双极晶体管的发射极连接到第一双极晶体管的基极，其中第二双极晶体管的基极和集电极连接到VSS。 添加第一和第二电流以产生第三电流，其被镜像以产生与第三电流成比例的第四电流。 第四电流通过第三电阻器传导以产生输出参考电压。

公开(公告)号：US08476971B2

公开(公告)日：2013-07-02

申请号：US12889492

申请日：2010-09-24

Applicant: Yung-Chow Peng ,  Wen-Shen Chou ,  Ching-Ho Chang ,  Wan-Te Chen

Inventor： Yung-Chow Peng ,  Wen-Shen Chou ,  Ching-Ho Chang ,  Wan-Te Chen

IPC: G06G7/12

CPC classification number: G09G3/3688 ,  G09G2310/027

Abstract: A driver utilizes selective biasing of the terminal of an operational amplifier to reduce offset in the operational amplifier output. Each operational amplifier input includes a differential input pair of transistors including a NMOS transistor and PMOS transistor. At low and high ends of the input voltage range these transistors are selectively and individually coupled to either a standard input or biased to be on so as to contribute offset for offset compensation. The transistors are biased in a conventional manner for input voltages between the low and high ends of the voltage range.

Abstract translation: 驱动器利用运算放大器的端子的选择性偏置来减小运算放大器输出中的偏移。 每个运算放大器输入包括包括NMOS晶体管和PMOS晶体管的差分输入对晶体管。 在输入电压范围的低端和高端，这些晶体管选择性地和单独地耦合到标准输入或偏置为导通，以便补偿偏移补偿。 晶体管以常规方式偏置，用于在电压范围的低端和高端之间的输入电压。

公开(公告)号：US20100141497A1

公开(公告)日：2010-06-10

申请号：US12331049

申请日：2008-12-09

Applicant: Robit Yang ,  Ying-Chi Hsu ,  You-Cheng Xiao ,  Wen-Shen Chou

Inventor： Robit Yang ,  Ying-Chi Hsu ,  You-Cheng Xiao ,  Wen-Shen Chou

IPC: H03M1/66

CPC classification number: H03M1/0651 ,  H03M1/0648 ,  H03M1/682 ,  H03M1/687 ,  H03M1/747

Abstract: A digital-to-analog converter (DAC) for converting a digital signal to an analog signal includes a first thermometer decoder and a second thermometer decoder. The first thermometer decoder is configured to decode most-significant bits (MSBs) of the digital signal to generate a first thermometer code. The second thermometer decoder is configured to decode middle bits of the digital signal to generate a second thermometer code. The DAC further includes a plurality of macro cells with each controlled by one bit of the first thermometer code. The plurality of macro cells is configured to provide a first analog signal according to the first thermometer code. The DAC further includes a macro cell configured to provide a second analog signal according to the second thermometer code. The macro cell is further configured to provide a third analog signal according to least-significant bits (LSBs) of the digital signal.

Abstract translation: 用于将数字信号转换为模拟信号的数模转换器（DAC）包括第一温度计解码器和第二温度计解码器。 第一温度计解码器被配置为解码数字信号的最高有效位（MSB），以产生第一温度计代码。 第二温度计解码器被配置为解码数字信号的中间位以产生第二温度计代码。 DAC还包括多个宏单元，每个宏单元由第一温度计代码的一位控制。 多个宏小区被配置为根据第一温度计代码提供第一模拟信号。 DAC还包括配置成根据第二温度计代码提供第二模拟信号的宏单元。 宏小区还被配置为根据数字信号的最低有效位（LSB）提供第三模拟信号。

公开(公告)号：US08719755B2

公开(公告)日：2014-05-06

申请号：US13562638

申请日：2012-07-31

Applicant: Wen-Shen Chou ,  Yung-Chow Peng ,  Chih-Chiang Chang ,  Chin-Hua Wen

Inventor： Wen-Shen Chou ,  Yung-Chow Peng ,  Chih-Chiang Chang ,  Chin-Hua Wen

IPC: G06F17/50

CPC classification number: G06F17/5068

Abstract: Among other things, one or more techniques for graded dummy insertion and a resulting array are provided herein. For example an array is a metal oxide semiconductor (MOS) array, a metal oxide metal (MOM) array, or a resistor array. In some embodiments, a first region and a second region are identified based on a density gradient between a first pattern density associated with the first region and a second pattern density associated with the second region. For example, the first pattern density and the second pattern density are gate densities and/or poly densities. To this end, a dummy region is inserted between the first region and the second region, the dummy region includes a graded pattern density based on a first adjacent pattern density and a second adjacent pattern density. In this manner, graded dummy insertion is provided, thus enhancing edge cell performance for an array, for example.

Abstract translation: 除此之外，本文提供了用于分级虚拟插入的一种或多种技术和所得到的阵列。 例如，阵列是金属氧化物半导体（MOS）阵列，金属氧化物金属（MOM）阵列或电阻阵列。 在一些实施例中，基于与第一区域相关联的第一图案密度与与第二区域相关联的第二图案密度之间的密度梯度来识别第一区域和第二区域。 例如，第一图案密度和第二图案密度是门密度和/或多密度。 为此，在第一区域和第二区域之间插入虚拟区域，虚拟区域包括基于第一相邻图案密度和第二相邻图案密度的渐变图案密度。 以这种方式，提供分级虚拟插入，从而提高阵列的边缘单元性能。