公开(公告)号：US20180048326A1

公开(公告)日：2018-02-15

申请号：US15652252

申请日：2017-07-18

Applicant: MEDIATEK INC.

Inventor： Pao-Cheng Chiu ,  Hung-Yi Hsieh

IPC: H03M3/00

CPC classification number: H03M3/322 ,  H03M1/066 ,  H03M3/422 ,  H03M3/436 ,  H03M3/458 ,  H03M3/464

Abstract: A delta-sigma modulator includes a receiving circuit, a loop filter, a quantizer, a dynamic element matching circuit and a digital to analog converter. The receiving circuit is arranged for receiving a feedback signal and an input signal to generate a summation signal. The loop filter is arranged for receiving the summation signal to generate a filtered summation signal. The quantizer is arranged for generating a digital output signal according to the filtered summation signal. The dynamic element matching circuit is arranged for receiving the digital output signal to generate a shaped digital output signal for shaping element mismatch. The digital to analog converter is arranged for performing a digital to analog converting operation upon a signal derived from the shaped digital output signal to generate the feedback signal to the receiving circuit, wherein clock signals used by the quantizer and the dynamic element matching circuit have different frequencies.

公开(公告)号：US09985645B2

公开(公告)日：2018-05-29

申请号：US15652252

申请日：2017-07-18

Applicant: MEDIATEK INC.

Inventor： Pao-Cheng Chiu ,  Hung-Yi Hsieh

IPC: H03M3/00

CPC classification number: H03M3/322 ,  H03M1/066 ,  H03M3/422 ,  H03M3/436 ,  H03M3/458 ,  H03M3/464

Abstract: A delta-sigma modulator includes a receiving circuit, a loop filter, a quantizer, a dynamic element matching circuit and a digital to analog converter. The receiving circuit is arranged for receiving a feedback signal and an input signal to generate a summation signal. The loop filter is arranged for receiving the summation signal to generate a filtered summation signal. The quantizer is arranged for generating a digital output signal according to the filtered summation signal. The dynamic element matching circuit is arranged for receiving the digital output signal to generate a shaped digital output signal for shaping element mismatch. The digital to analog converter is arranged for performing a digital to analog converting operation upon a signal derived from the shaped digital output signal to generate the feedback signal to the receiving circuit, wherein clock signals used by the quantizer and the dynamic element matching circuit have different frequencies.

公开(公告)号：US09154152B1

公开(公告)日：2015-10-06

申请号：US14576315

申请日：2014-12-19

Applicant: MediaTek Inc.

Inventor： Pao-Cheng Chiu ,  Wei-Hsin Tseng

IPC: H03M1/06 ,  H03M1/46 ,  H03M1/08 ,  H03M1/20

CPC classification number: H03M1/468 ,  H03M1/0607 ,  H03M1/08 ,  H03M1/1061

Abstract: Analog-to-digital-converters (ADC) are provided. The ADC contains a first capacitive digital-to-analog-converter (CDAC) and a control circuit. The CDAC, including n bit, is configured to connect a kth bit of the n bits to a first voltage reference to provide a first analog signal, convert the first analog signal into first digital code using 0th through (k−1)th bits that are less significant than the kth bit, connect the kth bit of the n bits to a second voltage reference to provide a second analog signal, and convert the second analog signal into second digital code using the 0th through (k−1)th bits that are less significant than the kth bit. The control circuit is configured to estimate a weight of the kth bit based on the first and second digital code.

Abstract translation: 提供模数转换器（ADC）。 ADC包含第一个电容数模转换器（CDAC）和一个控制电路。 包括n位的CDAC被配置为将n位的第k位连接到第一参考电压以提供第一模拟信号，使用第0到第（k-1）位将第一模拟信号转换为第一数字码， 比第k位更不重要，将n位的第k位连接到第二参考电压以提供第二模拟信号，并且使用第0到第（k-1）位将第二模拟信号转换为第二数字码， 不如第k位显着。 控制电路被配置为基于第一和第二数字码估计第k位的权重。

公开(公告)号：US20150131811A1

公开(公告)日：2015-05-14

申请号：US14601253

申请日：2015-01-21

Applicant: MEDIATEK INC.

Inventor： Tsung-Kai Kao ,  Pao-Cheng Chiu ,  Chien-Ming Chen

IPC: H03G3/34

CPC classification number: H03G3/348

Abstract: A signal output device includes: a control circuit for receiving at least a first input control signal and outputting an output control signal according to at least the first input control signal, wherein the first input control signal has a first signal segment followed by a second signal segment, and a voltage level of the first signal segment is unknown; and a driver circuit, operated according to a supply power, for receiving the output control signal from the control circuit; wherein a voltage of the supply power is settle before the second signal segment of the first input control signal is received by the control circuit; when the supply power is turned on, the driver circuit operates under a specific power state; and when the second signal segment of the first input control signal is received by the control circuit, the driver circuit keeps operating under the specific power state.

Abstract translation: 信号输出装置包括：控制电路，用于至少接收第一输入控制信号并根据至少第一输入控制信号输出输出控制信号，其中第一输入控制信号具有第一信号段和第二信号 段，第一信号段的电压电平未知; 以及驱动器电路，其根据供电功率进行操作，用于从所述控制电路接收所述输出控制信号; 其中在所述控制电路接收到所述第一输入控制信号的所述第二信号段之前，所述供电电压被稳定; 当电源接通时，驱动电路在特定功率状态下工作; 并且当控制电路接收到第一输入控制信号的第二信号段时，驱动电路在特定功率状态下保持运行。

公开(公告)号：US09008247B2

公开(公告)日：2015-04-14

申请号：US13912847

申请日：2013-06-07

Applicant: MediaTek Inc.

Inventor： Wei-Cheng Tang ,  Juiyuan Tsai ,  Pao-Cheng Chiu

IPC: H04B7/04 ,  H04W56/00

CPC classification number: H04B7/0413 ,  H04W56/0015

Abstract: A communication circuit and a communication device are provided. The communication circuit includes first, second, and third RF transceivers, first and second baseband transceivers, and first and second modem circuits. The first and second RF transceivers are configured to down-convert first and second RF signals for MIMO. The third RF transceiver is configured to down-convert a third RF signal for a second telecommunication technology. The first baseband transceiver is configured to digitize the down-converted first RF signal to output a first baseband signal. The second baseband transceiver is configured to digitize one of the down-converted second or third RF signals according to a selection signal to output a second baseband signal. The first modem circuit is configured to digitally process the first and second baseband signals using the MIMO technology. The second modem circuit is configured to digitally process the second baseband signal using the second telecommunication technology.

Abstract translation: 提供通信电路和通信设备。 通信电路包括第一，第二和第三RF收发器，第一和第二基带收发器以及第一和第二调制解调器电路。 第一和第二RF收发器被配置为对用于MIMO的第一和第二RF信号进行下变频。 第三RF收发器被配置为对第二电信技术的第三RF信号进行下变频。 第一基带收发器被配置为对下变频的第一RF信号进行数字化以输出第一基带信号。 第二基带收发器被配置为根据选择信号对下变频的第二或第三RF信号之一进行数字化，以输出第二基带信号。 第一调制解调器电路被配置为使用MIMO技术对第一和第二基带信号进行数字处理。 第二调制解调器电路被配置为使用第二电信技术对第二基带信号进行数字处理。