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公开(公告)号：US08363766B2
公开(公告)日：2013-01-29
申请号：US12134913
申请日：2008-06-06
IPC分类号： H04L7/00
摘要： A first input signal is received at a data input of first synchronizer, the first data input to be synchronized to a clock. A second input signal is received at a data input of second synchronizer, the second signal to be synchronized to the clock. Transitions are prevented from being received at a clock input of the first synchronizer and from being received at a the clock input of the second synchronizer in response to the first input signal having the same logic value as a first output signal at an output of the first synchronizer and the second input signal having the same logic value as a second output signal at an output of the second synchronizer.
摘要翻译： 在第一同步器的数据输入处接收第一输入信号，第一数据输入与时钟同步。 在第二同步器的数据输入处接收第二输入信号，第二信号被同步到时钟。 防止在第一同步器的时钟输入处接收到转换，并且响应于在第一同步器的输出处具有与第一输出信号相同的逻辑值的第一输入信号，在第二同步器的时钟输入处接收到转换 同步器和第二输入信号在第二同步器的输出处具有与第二输出信号相同的逻辑值。
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公开(公告)号：US20090304134A1
公开(公告)日：2009-12-10
申请号：US12134913
申请日：2008-06-06
摘要： A first input signal is received at a data input of first synchronizer, the first data input to be synchronized to a clock. A second input signal is received at a data input of second synchronizer, the second signal to be synchronized to the clock. Transitions are prevented from being received at a clock input of the first synchronizer and from being received at a the clock input of the second synchronizer in response to the first input signal having the same logic value as a first output signal at an output of the first synchronizer and the second input signal having the same logic value as a second output signal at an output of the second synchronizer.
摘要翻译： 在第一同步器的数据输入处接收第一输入信号，第一数据输入与时钟同步。 在第二同步器的数据输入处接收第二输入信号，第二信号被同步到时钟。 防止在第一同步器的时钟输入处接收到转换，并且响应于在第一同步器的输出处具有与第一输出信号相同的逻辑值的第一输入信号，在第二同步器的时钟输入处接收到转换 同步器和第二输入信号在第二同步器的输出处具有与第二输出信号相同的逻辑值。
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3.发明授权Circuitry for providing replica data transfer signal during DMA verify operations 失效在DMA验证操作期间提供复制数据传输信号的电路
公开(公告)号：US5442753A
公开(公告)日：1995-08-15
申请号：US163165
申请日：1993-12-07
申请人： Timothy K. Waldrop , Paul R. Culley
发明人： Timothy K. Waldrop , Paul R. Culley
CPC分类号： G06F3/0601 , G06F13/28 , G06F5/06 , G06F2003/0692
摘要： The present invention includes two variations of an apparatus which generate a version of the IORC* bus signal that is supplied to the read strobe input of a floppy disk controller that is asserted at the appropriate time during verify cycles between the floppy disk controller and a DMA controller. These designs allow an 82077 floppy disk controller to operate properly in FIFO mode when it is being used with software that does not require generation of this signal. The designs include use of a PAL and certain bus signal inputs to generate a signal which is asserted at the appropriate times during verify transfers. This signal is combined with the regular IORC* bus signal to produce the signal that is provided to the read strobe input of the floppy disk controller.
摘要翻译： 本发明包括一种装置的两个变体，该装置产生提供给软盘控制器的读选通输入的IORC *总线信号的版本，该软盘控制器在软盘控制器和DMA之间的验证周期期间在适当的时间被断言 控制器。 这些设计允许82077软盘控制器在与不需要生成此信号的软件一起使用时，以FIFO模式正常运行。 这些设计包括使用PAL和某些总线信号输入来产生在验证传输期间在适当时间被断言的信号。 该信号与常规IORC *总线信号组合，以产生提供给软盘控制器的读选通输入的信号。
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公开(公告)号：US06950897B2
公开(公告)日：2005-09-27
申请号：US09792833
申请日：2001-02-23
CPC分类号： G06F13/4004
摘要： A technique is disclosed for facilitating data processing in a computer system. The technique utilizes logic to implement a dual mode design for PCI/PCI-X computer systems that enables optimal efficiency in regardless of which mode the system is operating in. The technique involves the implementation of two sets of transmitting and receiving elements, one tuned to PCI protocol timing and the other to PCI-X protocol. Therefore, allowing the system to process both PCI and PCI-X transactions without adversely affecting the other functional mode. The technique also enables an operator to adjust the clock timing separately for each protocol without having a detrimental affect on the other operating protocol.
摘要翻译： 公开了一种用于促进计算机系统中的数据处理的技术。 该技术利用逻辑来实现PCI / PCI-X计算机系统的双模式设计，无论系统运行哪种模式，都能实现最佳效率。该技术涉及实现两组发送和接收元件，一种调谐到 PCI协议定时，另一个到PCI-X协议。 因此，允许系统处理PCI和PCI-X交易，而不会对其他功能模式产生不利影响。 该技术还使操作员可以分别调整每个协议的时钟定时，而不会对其他操作协议产生不利影响。
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5.发明授权Enhancing a PCI-X split completion transaction by aligning cachelines with an allowable disconnect boundary's ending address 有权通过将高速缓存行与可允许的断开边界的结束地址对齐来增强PCI-X拆分完成事务公开(公告)号：US06901467B2
公开(公告)日：2005-05-31
申请号：US09792867
申请日：2001-02-23
申请人： Paras A. Shah , Timothy K. Waldrop
发明人： Paras A. Shah , Timothy K. Waldrop
CPC分类号： G06F13/4022
摘要： A method for processing a PCI-X transaction in a bridge is disclosed, wherein data is retrieved from a memory device and is stored in a bridge then delivered to a requesting device. The method may comprise the acts of allocating a buffer in the bridge for the PCI-X transaction, retrieving data from a memory device, wherein the data comprises a plurality of cachelines, storing the plurality of cachelines in the buffer, wherein the plurality of cachelines are tracked and marked for delivery as the plurality of cachelines are received in the buffer, and delivering the plurality of cachelines to the requesting device in address order, the plurality of cachelines transmitted to the requesting device when one of the plurality of cachelines in the buffer aligns to an ending address of an allowable disconnect boundary (ADB) and the remaining cachelines are in address order.
摘要翻译： 公开了一种用于在桥中处理PCI-X事务的方法，其中从存储设备检索数据，并将其存储在桥接器中，然后传送到请求设备。 该方法可以包括在用于PCI-X事务的桥中分配缓冲器的动作，从存储器设备检索数据，其中数据包括多个高速缓存行，将多条高速缓存行存储在缓冲器中，其中多条高速缓存行 被跟踪并标记为递送，因为多个高速缓存行被接收在缓冲器中，并且以地址顺序将多条高速缓存线递送到请求设备，当缓冲器中的多个高速缓存行中的一条缓存 与可允许的断开边界（ADB）的结束地址对齐，其余高速缓存线以地址顺序。
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公开(公告)号：US5307476A
公开(公告)日：1994-04-26
申请号：US999470
申请日：1992-12-29
申请人： Timothy K. Waldrop , Paul R. Culley
发明人： Timothy K. Waldrop , Paul R. Culley
CPC分类号： G06F3/0601 , G06F13/28 , G06F5/06 , G06F2003/0692
摘要： The present invention includes two variations of an apparatus which generate a version of the IORC* bus signal that is supplied to the read strobe input of a floppy disk controller that is asserted at the appropriate time during verify cycles between the floppy disk controller and a DMA controller. These designs allow an 82077 floppy disk controller to operate properly in FIFO mode when it is being used with software that does not require generation of this signal. The designs include use of a PAL and certain bus signal inputs to generate a signal which is asserted at the appropriate times during verify transfers. This signal is combined with the regular IORC* bus signal to produce the signal that is provided to the read strobe input of the floppy disk controller.
摘要翻译： 本发明包括一种装置的两个变体，该装置产生提供给软盘控制器的读选通输入的IORC *总线信号的版本，该软盘控制器在软盘控制器和DMA之间的验证周期期间在适当的时间被断言 控制器。 这些设计允许82077软盘控制器在与不需要生成此信号的软件一起使用时，以FIFO模式正常运行。 这些设计包括使用PAL和某些总线信号输入来产生在验证传输期间在适当时间被断言的信号。 该信号与常规IORC *总线信号组合，以产生提供给软盘控制器的读选通输入的信号。
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