All-to-all connected oscillator networks for solving combinatorial optimization problems

    公开(公告)号:US11698945B2

    公开(公告)日:2023-07-11

    申请号:US16832056

    申请日:2020-03-27

    CPC classification number: G06F17/11 G06F17/12 G06F17/13

    Abstract: An analog computing system with coupled non-linear oscillators can solve complex combinatorial optimization problems using the weighted Ising model. The system is composed of a fully-connected LC oscillator network with low-cost electronic components and compatible with traditional integrated circuit technologies. Each LC oscillator, or node, in the network can be coupled to each other node in the array with a multiply and accumulate crossbar array or optical interconnects. When implemented with four nodes, the system performs with single-run ground state accuracies of 98% on randomized MAX-CUT problem sets with binary weights and 84% with five-bit weight resolutions. The four-node system can obtain solutions within five oscillator cycles with a time-to-solution that scales directly with oscillator frequency. A scaling analysis suggests that larger coupled oscillator networks may be used to solve computationally intensive problems faster and more efficiently than conventional algorithms.

    All electrical fully connected coupled oscillator Ising machine

    公开(公告)号:US11552595B2

    公开(公告)日:2023-01-10

    申请号:US17007649

    申请日:2020-08-31

    Abstract: Networks of superharmonic injection-locked (SHIL) electronic oscillators can be used to emulate Ising machines for solving difficult computational problems. The oscillators can be simulated or implemented in hardware (e.g., with LC oscillators) and are coupled to each other with links whose connection strengths are weighted according to the problem being solved. The oscillators' phases may be measured with respect to reference signal(s) from one or more reference oscillators, each of which emits a reference signal but does not receive input from any other oscillator. Sparsely connected networks of SHIL oscillators and reference oscillators can be used as Viterbi decoders that do not suffer from the information bottleneck between logic computational blocks and memory in digital computing systems. Sparsely connected networks of SHIL oscillators and reference oscillators can also be programmed to act as Boolean logic gates that operate in both forward and backward directions, enabling multipliers that can factor numbers.

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