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公开(公告)号：US09865503B2
公开(公告)日：2018-01-09
申请号：US15330781
申请日：2016-11-07
发明人： Eran Rotem , Rami Zemach , Itay Peled
CPC分类号： H01L21/82 , G06F17/5072 , H01L23/564 , H01L23/585 , H01L28/00
摘要： Aspects of the disclosure provide a method for semiconductor wafer manufacturing. The method includes utilizing a subset of lower level masks in a mask set to form multiple modular units of lower level circuit structures on a semiconductor wafer. The mask set includes the subset of lower level masks and at least a first subset of upper level masks and a second subset of upper level masks. The first subset of upper level masks defines intra-unit interconnections. The second subset of upper level masks defines both intra-unit interconnections and inter-unit interconnections. The method further includes selecting one of at least the first subset of upper level masks and the second subset of upper level masks based on a composition request of a final integrated circuit (IC) product and utilizing the selected subset of upper level masks to form upper level structures on the semiconductor wafer.
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公开(公告)号：US08861248B2
公开(公告)日：2014-10-14
申请号：US14221668
申请日：2014-03-21
发明人： Eran Rotem
CPC分类号： G11C5/147 , G01R31/3004 , G01R31/31935 , G11C5/14
摘要： Aspects of the disclosure provide an integrated circuit (IC) that is configured to have an increased yield. The IC includes a memory element configured to store a specific value determined based on a characteristic of the IC, and a controller configured to control an input regulator based on the specific value of the IC. The input regulator is operative to provide a regulated input to the IC during operation, such that the IC performance satisfies performance requirement.
摘要翻译： 本公开的方面提供了被配置为具有增加的产量的集成电路（IC）。 IC包括被配置为存储基于IC的特性确定的特定值的存储器元件，以及被配置为基于IC的特定值来控制输入调节器的控制器。 输入调节器可操作以在操作期间向IC提供稳定的输入，使得IC性能满足性能要求。
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公开(公告)号：US08705264B2
公开(公告)日：2014-04-22
申请号：US14045462
申请日：2013-10-03
发明人： Eran Rotem
IPC分类号： G11C17/00
CPC分类号： G11C5/147 , G01R31/3004 , G01R31/31935 , G11C5/14
摘要： Aspects of the disclosure provide an integrated circuit (IC) that is configured to have an increased yield. The IC includes a memory element configured to store a specific value determined based on a characteristic of the IC, and a controller configured to control an input regulator based on the specific value of the IC. The input regulator is operative to provide a regulated input to the IC during operation, such that the IC performance satisfies performance requirement.
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4.再颁专利公开(公告)号：USRE47250E1
公开(公告)日：2019-02-19
申请号：US14861218
申请日：2015-09-22
发明人： Eran Rotem
IPC分类号： G11C17/00 , G11C5/14 , G01R31/30 , G01R31/3193
摘要： Aspects of the disclosure provide an integrated circuit (IC) that is configured to have an increased yield. The IC includes a memory element configured to store a specific value determined based on a characteristic of the IC, and a controller configured to control an input regulator based on the specific value of the IC. The input regulator is operative to provide a regulated input to the IC during operation, such that the IC performance satisfies performance requirement.
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公开(公告)号：US20170133271A1
公开(公告)日：2017-05-11
申请号：US15330781
申请日：2016-11-07
发明人： Eran Rotem , Rami Zemach , Itay Peled
CPC分类号： H01L21/82 , G06F17/5072 , H01L23/564 , H01L23/585 , H01L28/00
摘要： Aspects of the disclosure provide a method for semiconductor wafer manufacturing. The method includes utilizing a subset of lower level masks in a mask set to form multiple modular units of lower level circuit structures on a semiconductor wafer. The mask set includes the subset of lower level masks and at least a first subset of upper level masks and a second subset of upper level masks. The first subset of upper level masks defines intra-unit interconnections. The second subset of upper level masks defines both intra-unit interconnections and inter-unit interconnections. The method further includes selecting one of at least the first subset of upper level masks and the second subset of upper level masks based on a composition request of a final integrated circuit (IC) product and utilizing the selected subset of upper level masks to form upper level structures on the semiconductor wafer.
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