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1.发明授权Digital logic buffer for converting single polarity analog signals to dual polarity analog signals 失效用于将单极性模拟信号转换为双极性模拟信号的数字逻辑缓冲器
公开(公告)号：US4450365A
公开(公告)日：1984-05-22
申请号：US302318
申请日：1981-09-14
CPC分类号： G06F17/10
摘要： A digital logic buffer device for generating dual polarity analog signals is described. In the presently preferred embodiment, buffer receives the positive polarity analog output of a digital-to-analog converter (V.sub.DAC), and a sign bit. If the sign bit indicates that a positive polarity is required, the buffer will output approximately V.sub.DAC. If a negative polarity is required, aproximately -V.sub.DAC will be generated.
摘要翻译： 描述用于产生双极性模拟信号的数字逻辑缓冲器件。 在当前优选的实施例中，缓冲器接收数模转换器（VDAC）的正极性模拟输出和符号位。 如果符号位表示需要正极性，则缓冲器将输出大约VDAC。 如果需要负极性，则会产生近似的-VDAC。
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2.发明授权
公开(公告)号：US4771671A
公开(公告)日：1988-09-20
申请号：US1813
申请日：1987-01-08
申请人： Marcian E. Hoff, Jr.
发明人： Marcian E. Hoff, Jr.
CPC分类号： G10H1/366 , G10H3/125 , G10H2210/066 , G10H2210/331 , G10H2210/541
摘要： An electronic entertainment device which allows an untrained vocalist or instrumentalist to easily synthesize an instrumental lead, and optionally, one or more harmonies, simultaneous with the lead, playing along with predefined background musical sequences. While the background parts to a song are being played by the device, or any outside musical player, the user plays the melody, or "lead", by humming, singing, whistling, or operating any tone-producing device, such as a musical instrument, into the device. The device then identifies the pitch, compares it with a table of allowable pitches, as dictated by predefined data associated with the background music, chooses an appropriate output tone, and drives a music synthesizer to play the chosen instrument at the determined pitch, in accordance with the allowable pitches. The note which is produced by the device is one which sounds pleasing in the context of the musical background. The device facilitates an active involvement in music expression without a need for well developed skills as a vocalist or instrumentalist.
摘要翻译： 一种电子娱乐装置，其允许未经训练的歌手或乐器演奏者容易地与乐器导线合成，以及可选地与导线同时进行一个或多个和声，与预定义的背景音乐序列一起播放。 虽然设备或任何外部音乐播放器正在播放歌曲的背景部分，但是用户通过哼唱，唱歌，吹口哨或操作诸如音乐的任何音调产生设备来播放旋律或“引导” 仪器，进入设备。 然后，设备识别音调，将其与允许音高的表进行比较，如与背景音乐相关联的预定义数据所规定的，选择适当的输出音，并且驱动音乐合成器以所确定的音调播放所选择的乐器，按照 具有允许的间距。 由设备产生的音符是在音乐背景的背景下听起来令人愉快的音符。 该设备有助于积极参与音乐表达，而不需要作为歌手或乐器演奏者的良好发展的技能。
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公开(公告)号：US4100437A
公开(公告)日：1978-07-11
申请号：US709719
申请日：1976-07-29
申请人： Marcian E. Hoff, Jr.
发明人： Marcian E. Hoff, Jr.
摘要： An MOS integrated circuit for providing a stable reference voltage. The voltage thresholds of an enhancement mode transistor and depletion mode transistor are substracted to provide the stable reference potential. The reference potential is stable for both temperature and power supply variations, including variations in a substrate biasing potential.
摘要翻译： 用于提供稳定参考电压的MOS集成电路。 减小增强型晶体管和耗尽型晶体管的电压阈值以提供稳定的参考电位。 参考电位对于温度和电源变化都是稳定的，包括衬底偏置电位的变化。
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">4.发明授权MOS Digital-to-analog converter with resistor chain using compensating "dummy" metal contacts 失效MOS数模转换器，具有使用补偿“虚拟”金属触点的电阻链
公开(公告)号：US4398207A
公开(公告)日：1983-08-09
申请号：US263040
申请日：1981-05-12
CPC分类号： H01L27/0802 , H03M1/74 , Y10S257/925
摘要： An MOS integrated circuit digital-to-analog converter employing a plurality of generally parallel resistance strings. Decoding means and switching means provide an analog output from the resistance strings, this output passes through only two switches. The resistance strings may be closely fabricated on a substrate, thereby reducing the effects of processing variations. A unique layout for the converter array minimizes the effects of masking misalignments.
摘要翻译： 一种使用多个大致平行的电阻串的MOS集成电路数模转换器。 解码装置和开关装置提供来自电阻串的模拟输出，该输出仅通过两个开关。 可以在衬底上紧密地制造电阻串，从而减少处理变化的影响。 转换器阵列的独特布局最大限度地减少了屏蔽不对准的影响。
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公开(公告)号：US4250570A
公开(公告)日：1981-02-10
申请号：US867779
申请日：1978-01-09
CPC分类号： G11C29/781
摘要： A redundant memory circuit for a memory array in which the memory has a preselected number of rows and columns having addresses associated therewith and decoders coupled thereto and one or more redundant rows or columns having initially unspecified addresses associated therewith and redundant decoders coupled thereto. The redundant memory circuit programs the redundant decoders coupled to the redundant rows or columns having initially unspecified addresses to match the addresses of defective rows or columns having addresses associated therewith and disables one or more of the defective rows or columns having addresses associated therewith.
摘要翻译： 一种用于存储器阵列的冗余存储器电路，其中存储器具有预选数量的行和具有与其相关联的地址的列和与其耦合的解码器以及具有与之相关联的初始未指定地址的一个或多个冗余行或列，以及与其耦合的冗余解码器。 冗余存储器电路编程耦合到具有最初未指定地址的冗余行或列的冗余解码器以匹配具有与其相关联的地址的缺陷行或列的地址，并且禁用具有与其相关联的地址的一个或多个缺陷行或列。
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公开(公告)号：US4319325A
公开(公告)日：1982-03-09
申请号：US120701
申请日：1980-02-11
CPC分类号： G06F17/10
摘要： An integrated circuit processor real time processing of analog signals is described. The programmable processor duplicates filters, waveform generators and non-linear functions, such as rectification, with a high degree of stability and at a relatively low cost. A two-port, random-access memory provides inputs to an arithmetic logic unit (ALU). One of these inputs is coupled through a scaler (shifter). This scaler in conjunction with the ALU provides efficient multiplication, particularly by coefficients. ALU overflows are handled in an unusual manner to eliminate additional processing time for overflows. In a typical application, the one chip processor, with its 192-word program, samples an input analog signal at the rate of 13,020 Hz and detects the 8 tones used in telephony.
摘要翻译： 描述了模拟信号的集成电路处理器实时处理。 可编程处理器以高度的稳定性和相对较低的成本重复滤波器，波形发生器和非线性功能，例如整流。 两端口随机存取存储器向算术逻辑单元（ALU）提供输入。 这些输入之一通过缩放器（移位器）耦合。 这种与ALU结合的缩放器提供了有效的乘法，特别是通过系数。 ALU溢出以不寻常的方式处理，以消除溢出的额外处理时间。 在典型的应用中，单芯片处理器以其192个字节的程序对13,020 Hz的输入模拟信号进行采样，并检测电话中使用的8个音调。
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公开(公告)号：US4146882A
公开(公告)日：1979-03-27
申请号：US717442
申请日：1976-08-24
CPC分类号： H03M1/78
摘要： An MOS integrated circuit digital-to-analog converter employing a plurality of generally parallel resistance strings. Decoding means and switching means provide an analog output from the resistance strings, this output passes through only two switches. The resistance strings may be closely fabricated on a substrate, thereby reducing the effects of processing variations. A unique layout for the converter array minimizes the effects of masking misalignments.
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公开(公告)号：US4007452A
公开(公告)日：1977-02-08
申请号：US599709
申请日：1975-07-28
申请人： Marcian E. Hoff, Jr.
发明人： Marcian E. Hoff, Jr.
IPC分类号： H01L21/82 , G06F12/06 , G11C29/00 , H01L21/8247 , H01L29/788 , H01L29/792 , G11C17/00
CPC分类号： G11C29/78 , G06F12/0676 , G11C29/006
摘要： A system and method for interconnecting a plurality of separate memories (on other circuits) on a wafer so as to electrically exclude defective memories and include operative memories. A single discretionary connection is associated with each of the separate memories and such connection is made (or broken) after a memory is tested. In addition to a bidirectional memory bus used for input/output data and addresses, the wafer includes a separate identity bus used to define the memory organization. The identity bus is interconnected by a plurality of incrementers, one associated with each memory. The signal on the identity bus is incremented by useable memories and such signal is compared to an address on the bidirectional memory bus to select memories in an organized manner.
摘要翻译： 一种用于互连晶片上的多个分离的存储器（在其他电路上）的系统和方法，以便电排除有缺陷的存储器并且包括操作存储器。 单独的自由连接与每个单独的存储器相关联，并且在测试存储器之后进行这种连接（或断开）。 除了用于输入/输出数据和地址的双向存储器总线之外，晶片还包括用于定义存储器组织的单独标识总线。 身份总线通过多个递增器互连，一个与每个存储器相关联。 身份总线上的信号由可用的存储器增加，并且将该信号与双向存储器总线上的地址进行比较，以有组织的方式选择存储器。
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