公开(公告)号：US20070096287A1

公开(公告)日：2007-05-03

申请号：US11582328

申请日：2006-10-18

申请人： Makoto Araki ,  Masakatsu Goto ,  Shigeru Nakamura

发明人： Makoto Araki ,  Masakatsu Goto ,  Shigeru Nakamura

IPC分类号： H01L23/02

CPC分类号： H01L25/105 ,  H01L24/81 ,  H01L25/50 ,  H01L2224/13144 ,  H01L2224/16 ,  H01L2224/16225 ,  H01L2224/32225 ,  H01L2224/73204 ,  H01L2224/73253 ,  H01L2224/8121 ,  H01L2224/81815 ,  H01L2224/83192 ,  H01L2225/1023 ,  H01L2225/1058 ,  H01L2924/01019 ,  H01L2924/01078 ,  H01L2924/01079 ,  H01L2924/15311 ,  H01L2924/15331 ,  H01L2924/3511 ,  H01L2924/00

摘要： Packaging performance of a semiconductor device is improved. A semiconductor device has a package substrate having a base material formed of resin; a semiconductor chip mounted on a main surface of the package substrate; a tape substrates being stacked on the package substrate in several stages, and electrically connected to a substrate at a lower stage via a plurality of solder balls; a second-stage chip, third-stage chip, and fourth-stage chip mounted on the tape substrates at respective stages; and a plurality of solder balls provided on a back surface of the package substrate; wherein a sealing body, which resin-seals the semiconductor chip and is formed by resin molding, is formed on a main surface of a package substrate disposed at the lowest stage, and the sealing body is disposed between the package substrate at the lowest stage and the tape substrate stacked thereon.

摘要翻译： 提高了半导体器件的封装性能。 半导体器件具有由树脂形成的基材的封装基板; 安装在所述封装基板的主表面上的半导体芯片; 带状基板分几层堆叠在封装基板上，并通过多个焊球在较低级电连接到基板; 第二级芯片，第三级芯片和第四级芯片，分别安装在磁带基板上; 以及设置在所述封装基板的背面上的多个焊球; 其特征在于，在设置在最下层的封装基板的主表面上形成有通过树脂成形形成树脂密封半导体芯片的密封体，密封体设置在最底层的封装基板和 所述带基材堆叠在其上。

公开(公告)号：US08035979B2

公开(公告)日：2011-10-11

申请号：US12966251

申请日：2010-12-13

申请人： Yutaka Yoshino ,  Takahiro Shirai ,  Shinji Kadono ,  Mineo Kawamoto ,  Minoru Enomoto ,  Masakatsu Goto ,  Makoto Araki ,  Naoki Toda

发明人： Yutaka Yoshino ,  Takahiro Shirai ,  Shinji Kadono ,  Mineo Kawamoto ,  Minoru Enomoto ,  Masakatsu Goto ,  Makoto Araki ,  Naoki Toda

IPC分类号： H05K1/18

CPC分类号： H01L23/5389 ,  H01L25/105 ,  H01L2224/16237 ,  H01L2224/48091 ,  H01L2224/48227 ,  H01L2224/48228 ,  H01L2224/73204 ,  H01L2224/73265 ,  H01L2224/82039 ,  H01L2924/01004 ,  H01L2924/01078 ,  H01L2924/01079 ,  H01L2924/12044 ,  H01L2924/3011 ,  H05K1/023 ,  H05K1/186 ,  H05K3/4602 ,  H05K3/4623 ,  H05K3/4652 ,  H05K2201/0187 ,  H05K2201/10674 ,  Y10T29/49146 ,  H01L2924/00014

摘要： A printed wiring board includes a built-in semiconductor element. A protective film is formed on a semiconductor element-mounted surface of a base substrate to which the built-in semiconductor element is connected to protect the semiconductor element-mounted surface excepting a mounting pad. Upper and side surfaces of the built-in semiconductor element are covered with a first insulating film formed by filling a sealing material. The first insulating film is covered with a second insulating film formed of an insulating resin melted from an insulating layer that is provided in side and upper portions of the built-in semiconductor element.

摘要翻译： 印刷电路板包括内置的半导体元件。 在与内置半导体元件连接的基底基板的半导体元件安装面上形成保护膜，以保护除了安装焊盘之外的半导体元件安装表面。 通过填充密封材料形成的第一绝缘膜覆盖内置半导体元件的上表面和侧表面。 第一绝缘膜被由设置在内置半导体元件的侧部和上部的绝缘层熔化的绝缘树脂形成的第二绝缘膜覆盖。

公开(公告)号：US07894200B2

公开(公告)日：2011-02-22

申请号：US11913559

申请日：2006-11-28

申请人： Yutaka Yoshino ,  Takahiro Shirai ,  Shinji Kadono ,  Mineo Kawamoto ,  Minoru Enomoto ,  Masakatsu Goto ,  Makoto Araki ,  Naoki Toda

发明人： Yutaka Yoshino ,  Takahiro Shirai ,  Shinji Kadono ,  Mineo Kawamoto ,  Minoru Enomoto ,  Masakatsu Goto ,  Makoto Araki ,  Naoki Toda

IPC分类号： H05K1/18

CPC分类号： H01L23/5389 ,  H01L25/105 ,  H01L2224/16237 ,  H01L2224/48091 ,  H01L2224/48227 ,  H01L2224/48228 ,  H01L2224/73204 ,  H01L2224/73265 ,  H01L2224/82039 ,  H01L2924/01004 ,  H01L2924/01078 ,  H01L2924/01079 ,  H01L2924/12044 ,  H01L2924/3011 ,  H05K1/023 ,  H05K1/186 ,  H05K3/4602 ,  H05K3/4623 ,  H05K3/4652 ,  H05K2201/0187 ,  H05K2201/10674 ,  Y10T29/49146 ,  H01L2924/00014

摘要： The present invention provides a printed wiring board with a built-in semiconductor element in which an insufficient or excessive amount of filled sealing material does not affect excellent adhesion of the printed wiring board to an overlying wiring board. The printed wiring board with a built-in semiconductor element comprises a built-in semiconductor element, in which at least the lower surface, the upper surface, or the side surface of the semiconductor element is covered with an insulating film, and an insulating layer is provided in the side and upper portions of the semiconductor element. There is also provided a process for producing a printed wiring board with a built-in semiconductor element, comprising the steps of mounting a semiconductor element on a base substrate and covering at least the lower surface, the upper surface, or the side surface of the semiconductor element with an insulating film, disposing and stacking a semicured insulating sheet in the side portion of the semiconductor element, and disposing and stacking a semicured insulating sheet in the upper portion of the semiconductor element.

摘要翻译： 本发明提供一种具有内置半导体元件的印刷电路板，其中填充的密封材料的量不足或过量不会影响印刷电路板对上覆布线板的优异的粘附性。 具有内置半导体元件的印刷线路板包括内置半导体元件，其中至少半导体元件的下表面，上表面或侧表面被绝缘膜覆盖，绝缘层 设置在半导体元件的侧部和上部。 还提供了一种用于制造具有内置半导体元件的印刷线路板的方法，包括以下步骤：将半导体元件安装在基底基板上，并且至少覆盖基底基板的下表面，上表面或侧表面 具有绝缘膜的半导体元件，在半导体元件的侧部设置和层叠半固化绝缘片，并且在半导体元件的上部设置和层叠半固化绝缘片。

公开(公告)号：US20110090657A1

公开(公告)日：2011-04-21

申请号：US12966251

申请日：2010-12-13

申请人： Yutaka YOSHINO ,  Takahiro Shirai ,  Shinji Kadono ,  Mineo Kawamoto ,  Minoru Enomoto ,  Masakatsu Goto ,  Makoto Araki ,  Naoki Toda

发明人： Yutaka YOSHINO ,  Takahiro Shirai ,  Shinji Kadono ,  Mineo Kawamoto ,  Minoru Enomoto ,  Masakatsu Goto ,  Makoto Araki ,  Naoki Toda

IPC分类号： H05K1/18

CPC分类号： H01L23/5389 ,  H01L25/105 ,  H01L2224/16237 ,  H01L2224/48091 ,  H01L2224/48227 ,  H01L2224/48228 ,  H01L2224/73204 ,  H01L2224/73265 ,  H01L2224/82039 ,  H01L2924/01004 ,  H01L2924/01078 ,  H01L2924/01079 ,  H01L2924/12044 ,  H01L2924/3011 ,  H05K1/023 ,  H05K1/186 ,  H05K3/4602 ,  H05K3/4623 ,  H05K3/4652 ,  H05K2201/0187 ,  H05K2201/10674 ,  Y10T29/49146 ,  H01L2924/00014

摘要： A printed wiring board includes a built-in semiconductor element. A protective film is formed on a semiconductor element-mounted surface of a base substrate to which the built-in semiconductor element is connected to protect the semiconductor element-mounted surface excepting a mounting pad. Upper and side surfaces of the built-in semiconductor element are covered with a first insulating film formed by filling a sealing material. The first insulating film is covered with a second insulating film formed of an insulating resin melted from an insulating layer that is provided in side and upper portions of the built-in semiconductor element.

摘要翻译： 印刷电路板包括内置的半导体元件。 在与内置半导体元件连接的基底基板的半导体元件安装面上形成保护膜，以保护除了安装焊盘之外的半导体元件安装表面。 通过填充密封材料形成的第一绝缘膜覆盖内置半导体元件的上表面和侧表面。 第一绝缘膜被由设置在内置半导体元件的侧部和上部的绝缘层熔化的绝缘树脂形成的第二绝缘膜覆盖。

公开(公告)号：US08377752B2

公开(公告)日：2013-02-19

申请号：US13019926

申请日：2011-02-02

申请人： Masakatsu Goto ,  Minoru Enomoto

发明人： Masakatsu Goto ,  Minoru Enomoto

IPC分类号： H01L21/00

CPC分类号： H01L24/81 ,  H01L23/3121 ,  H01L23/49816 ,  H01L23/5389 ,  H01L23/552 ,  H01L24/73 ,  H01L25/105 ,  H01L25/16 ,  H01L2224/16225 ,  H01L2224/2919 ,  H01L2224/32145 ,  H01L2224/32225 ,  H01L2224/45144 ,  H01L2224/48227 ,  H01L2224/73204 ,  H01L2224/73253 ,  H01L2224/73265 ,  H01L2224/81191 ,  H01L2224/83192 ,  H01L2225/1035 ,  H01L2225/1058 ,  H01L2924/01005 ,  H01L2924/01006 ,  H01L2924/01029 ,  H01L2924/01033 ,  H01L2924/01038 ,  H01L2924/01046 ,  H01L2924/01051 ,  H01L2924/01064 ,  H01L2924/01075 ,  H01L2924/01077 ,  H01L2924/01078 ,  H01L2924/01079 ,  H01L2924/014 ,  H01L2924/1306 ,  H01L2924/13091 ,  H01L2924/14 ,  H01L2924/15311 ,  H01L2924/15331 ,  H01L2924/181 ,  H01L2924/19105 ,  H01L2924/3025 ,  H01L2924/00012 ,  H01L2924/00

摘要： In regard to a semiconductor device having a multilayered wiring board where a semiconductor chip is embedded inside, a technology which allows the multilayered wiring board to be made thinner is provided. A feature of the present invention is that, in a semiconductor device where bump electrodes are formed over a main surface (element forming surface) of a semiconductor chip embedded in a chip-embedded wiring board, an insulating film is formed over a back surface (a surface on the side opposite to the main surface) of the semiconductor chip. As a result, it becomes unnecessary to form a prepreg over the back surface of the semiconductor chip. Therefore, an effect of thinning the chip-embedded wiring board in which the semiconductor chip is embedded is obtained.

摘要翻译： 关于具有嵌入半导体芯片的多层布线基板的半导体器件，提供了使多层布线基板制成薄型化的技术。 本发明的特征在于，在埋设在芯片嵌入式布线基板上的半导体芯片的主表面（元件形成面）上形成凸起电极的半导体器件中，绝缘膜形成在背面（ 半导体芯片的与主表面相对的一侧的表面）。 结果，不需要在半导体芯片的背面上形成预浸料。 因此，获得了嵌入半导体芯片的芯片嵌入式布线基板的薄型化的效果。

公开(公告)号：US5910010A

公开(公告)日：1999-06-08

申请号：US732215

申请日：1997-02-18

申请人： Hirotaka Nishizawa ,  Tomoyoshi Miura ,  Ichirou Anjou ,  Masamichi Ishihara ,  Masahiro Yamamura ,  Sadao Morita ,  Takashi Araki ,  Kiyoshi Inoue ,  Toshio Sugano ,  Tetsuji Kohara ,  Toshio Yamada ,  Yasushi Sekine ,  Yoshiaki Anata ,  Masakatsu Goto ,  Norihiko Kasai ,  Shinobu Takeura ,  Mutsuo Tsukuda ,  Yasunori Yamaguchi ,  Jiro Sawada ,  Hidetoshi Iwai ,  Seiichiro Tsukui ,  Tadao Kaji ,  Noboru Shiozawa

发明人： Hirotaka Nishizawa ,  Tomoyoshi Miura ,  Ichirou Anjou ,  Masamichi Ishihara ,  Masahiro Yamamura ,  Sadao Morita ,  Takashi Araki ,  Kiyoshi Inoue ,  Toshio Sugano ,  Tetsuji Kohara ,  Toshio Yamada ,  Yasushi Sekine ,  Yoshiaki Anata ,  Masakatsu Goto ,  Norihiko Kasai ,  Shinobu Takeura ,  Mutsuo Tsukuda ,  Yasunori Yamaguchi ,  Jiro Sawada ,  Hidetoshi Iwai ,  Seiichiro Tsukui ,  Tadao Kaji ,  Noboru Shiozawa

IPC分类号： H01L21/56 ,  H01L21/98 ,  H01L23/495 ,  H01L25/065 ,  H01L21/52 ,  H01L21/58 ,  H01L21/60

CPC分类号： H01L24/06 ,  H01L21/565 ,  H01L23/4951 ,  H01L23/49575 ,  H01L25/0657 ,  H01L25/50 ,  H01L2224/04042 ,  H01L2224/05554 ,  H01L2224/06136 ,  H01L2224/32245 ,  H01L2224/45015 ,  H01L2224/45144 ,  H01L2224/48091 ,  H01L2224/4826 ,  H01L2224/49171 ,  H01L2224/73215 ,  H01L2225/06527 ,  H01L2225/06551 ,  H01L2225/06582 ,  H01L2225/06586 ,  H01L2225/06589 ,  H01L24/45 ,  H01L24/48 ,  H01L24/49 ,  H01L2924/01004 ,  H01L2924/01005 ,  H01L2924/01006 ,  H01L2924/01013 ,  H01L2924/01014 ,  H01L2924/01019 ,  H01L2924/01023 ,  H01L2924/01028 ,  H01L2924/01029 ,  H01L2924/01033 ,  H01L2924/01039 ,  H01L2924/01042 ,  H01L2924/01046 ,  H01L2924/0105 ,  H01L2924/01055 ,  H01L2924/01058 ,  H01L2924/01075 ,  H01L2924/01076 ,  H01L2924/01078 ,  H01L2924/01079 ,  H01L2924/01082 ,  H01L2924/01322 ,  H01L2924/014 ,  H01L2924/12042 ,  H01L2924/13091 ,  H01L2924/14 ,  H01L2924/15153 ,  H01L2924/15165 ,  H01L2924/181 ,  H01L2924/1815 ,  H01L2924/19041 ,  H01L2924/3011 ,  H01L2924/3025 ,  H01L2924/351

摘要： A method of manufacturing a semiconductor integrated circuit device includes the steps of constructing a plurality of lead frames having leads which each include an inner portion and an outer portion and electrically connecting a semiconductor chip to the inner portions of the leads of each frame. The lead frames are then stacked one above each other to form a vertical stack and plates are then inserted between each of the lead frames with each plate having an opening in the center whereby a central cavity is formed in the stack. The stack is then placed between a top mold member and a bottom mold member and a resin is injected into the central cavity whereupon the resin is cured to form a single resin package encapsulating the semiconductor chips. The resin package is then released from the mold members.

摘要翻译： PCT No.PCT / JP95 / 00662 Sec。 371日期1997年2月18日 102（e）日期1997年2月18日PCT提交1995年4月5日PCT公布。 WO95 / 29506 PCT公开号 日期：1995年11月2日制造半导体集成电路器件的方法包括以下步骤：构造多个引线框架，引线框架各自包括内部部分和外部部分，并将半导体芯片电连接到引线的内部 每一帧。 然后将引线框架彼此堆叠以形成垂直堆叠，然后将板在每个引线框架之间插入，每个板在中心具有开口，由此在堆叠中形成中心空腔。 然后将堆叠放置在顶模构件和底模构件之间，并将树脂注入到中心腔中，由此树脂固化以形成封装半导体芯片的单个树脂封装。 然后将树脂包装从模具部件中释放出来。