公开(公告)号：US07656237B2

公开(公告)日：2010-02-02

申请号：US11002559

申请日：2004-12-02

Applicant: Mack Wayne Riley ,  Daniel Lawrence Stasiak ,  Michael Fan Wang ,  Stephen Douglas Weitzel

Inventor： Mack Wayne Riley ,  Daniel Lawrence Stasiak ,  Michael Fan Wang ,  Stephen Douglas Weitzel

IPC: H03L7/095

CPC classification number: G06F1/04 ,  G06F1/3203 ,  G06F1/3237 ,  H03L7/06 ,  Y02D10/126 ,  Y02D10/128 ,  Y10S331/02

Abstract: An apparatus, a method, and a computer program are provided to gate a Phased Locked Loop (PLL). In microprocessors, the clock distribution system can account for a substantial amount of power consumption. Gating the PLLs, however, has been difficult because of the usual requirement for a separate clock for control logic and because the PLL requires timed to reacquire phase/frequency lock. Therefore, lock detection logic can be employed to allow the PLL to reacquire phase/frequency lock. Additionally, signals from external devices and the processor can be employed to gate the PLL and allow the processor to be awakened without a need for a separate clock.

Abstract translation: 提供了一种设备，方法和计算机程序来对相位锁定环路（PLL）进行门控。 在微处理器中，时钟分配系统可以占用大量的功耗。 然而，门控门限是困难的，因为控制逻辑需要单独的时钟，因为PLL需要定时重新获取相位/频率锁定。 因此，可以采用锁定检测逻辑来允许PLL重新获取相位/频率锁定。 此外，可以采用来自外部设备和处理器的信号来门控PLL，并且允许处理器被唤醒而无需单独的时钟。

公开(公告)号：US20090058503A1

公开(公告)日：2009-03-05

申请号：US11847390

申请日：2007-08-30

Applicant: Michael Joseph Genden ,  Mack Wayne Riley

Inventor： Michael Joseph Genden ,  Mack Wayne Riley

IPC: H01H37/76

CPC classification number: G11C17/18 ,  H01H85/0241

Abstract: An eFuse system that includes a mechanism that bridges banks of eFuses and allows the banks of eFuses to be placed any distance from each other. The bridging of the eFuse banks is transparent to compression and encode programming algorithm and hardware decode mechanisms. Thus, by using the mechanism for bridging gaps between eFuse banks, an eFuse subsystem with several banks distributed on an integrated circuit chip appears to be a single large eFuse bank to the encode/decode mechanisms of the integrated circuit. Additionally, with this mechanism, eFuse banks can be easily added or deleted.

Abstract translation: 一个eFuse系统，其中包括一个桥接eFus网络的机制，并允许efuses库彼此间隔一定距离。 eFuse银行的桥接对于压缩和编码编程算法和硬件解码机制是透明的。 因此，通过使用用于桥接eFuse存储体之间的间隙的机制，分布在集成电路芯片上的多个存储体的eFuse子系统似乎是集成电路的编码/解码机制的单个大型eFuse存储体。 另外，利用这种机制，可以轻松添加或删除eFuse银行。

公开(公告)号：US07284138B2

公开(公告)日：2007-10-16

申请号：US11002551

申请日：2004-12-02

Applicant: Mack Wayne Riley ,  Daniel Lawrence Stasiak ,  Michael Fan Wang ,  Stephen Douglas Weitzel

Inventor： Mack Wayne Riley ,  Daniel Lawrence Stasiak ,  Michael Fan Wang ,  Stephen Douglas Weitzel

IPC: G06F1/00

CPC classification number: G06F1/3203 ,  G06F1/3237 ,  Y02D10/128

Abstract: An apparatus, a method, and a computer program are provided to disable clock distribution. In microprocessors, the clock distribution system can account for a substantial amount of power consumption. Disabling the clock distribution system, however, has been difficult because of the usual requirement for a separate clock for control logic. Therefore, combinational logic can be employed to disrupt the clock distribution and allow a processor to be awakened without a need for a separate clock.

Abstract translation: 提供了一种装置，方法和计算机程序来禁止时钟分配。 在微处理器中，时钟分配系统可以占用大量的功耗。 然而，禁用时钟分配系统是困难的，因为通常需要用于控制逻辑的单独时钟。 因此，可以采用组合逻辑来中断时钟分配，并且允许处理器被唤醒而不需要单独的时钟。

公开(公告)号：US07702944B2

公开(公告)日：2010-04-20

申请号：US12352108

申请日：2009-01-12

Applicant: Nathan Chelstrom ,  Mack Wayne Riley ,  Michael Fan Wang ,  Stephen Douglas Weitzel

Inventor： Nathan Chelstrom ,  Mack Wayne Riley ,  Michael Fan Wang ,  Stephen Douglas Weitzel

IPC: G06F1/00 ,  H03L7/00

CPC classification number: G06F1/3203 ,  G06F1/08 ,  G06F1/324 ,  Y02D10/126

Abstract: The present invention provides for reducing current spikes in a circuit when changing clocking frequencies. A first frequency is applied to a clock distribution network. A final frequency is selected. The first frequency is applied to a logic element over the clock distribution network. A hold signal is applied to the logic element. The clock rate of the clock distribution network is changed from the first frequency to the final frequency. The hold signal is unapplied to the logic element.

Abstract translation: 本发明提供了在改变时钟频率时减少电路中的电流尖峰。 第一个频率被应用到时钟分配网络。 选择最终频率。 第一个频率通过时钟分配网络应用于逻辑元件。 保持信号被施加到逻辑元件。 时钟分配网络的时钟速率从第一个频率改变到最后的频率。 保持信号未应用于逻辑元件。

公开(公告)号：US20090119552A1

公开(公告)日：2009-05-07

申请号：US12352108

申请日：2009-01-12

Applicant: Nathan Chelstrom ,  Mack Wayne Riley ,  Michael Fan Wang ,  Stephen Douglas Weitzel

Inventor： Nathan Chelstrom ,  Mack Wayne Riley ,  Michael Fan Wang ,  Stephen Douglas Weitzel

IPC: G06F11/00

CPC classification number: G06F1/3203 ,  G06F1/08 ,  G06F1/324 ,  Y02D10/126

Abstract: The present invention provides for reducing current spikes in a circuit when changing clocking frequencies. A first frequency is applied to a clock distribution network. A final frequency is selected. The first frequency is applied to a logic element over the clock distribution network. A hold signal is applied to the logic element. The clock rate of the clock distribution network is changed from the first frequency to the final frequency. The hold signal is unapplied to the logic element.

Abstract translation: 本发明提供了在改变时钟频率时减少电路中的电流尖峰。 第一个频率被应用到时钟分配网络。 选择最终频率。 第一个频率通过时钟分配网络应用于逻辑元件。 保持信号被施加到逻辑元件。 时钟分配网络的时钟速率从第一个频率改变到最后的频率。 保持信号未应用于逻辑元件。

公开(公告)号：US07516350B2

公开(公告)日：2009-04-07

申请号：US10937689

申请日：2004-09-09

Applicant: Nathan Chelstrom ,  Mack Wayne Riley ,  Michael Fan Wang ,  Stephen Douglas Weitzel

Inventor： Nathan Chelstrom ,  Mack Wayne Riley ,  Michael Fan Wang ,  Stephen Douglas Weitzel

IPC: G06F1/00 ,  H03L7/00

CPC classification number: G06F1/3203 ,  G06F1/08 ,  G06F1/324 ,  Y02D10/126

Abstract: The present invention provides for reducing current spikes in a circuit when changing clocking frequencies. A first frequency is applied to a clock distribution network. A final frequency is selected. The first frequency is applied to a logic element over the clock distribution network. A hold signal is applied to the logic element. The clock rate of the clock distribution network is changed from the first frequency to the final frequency. The hold signal is unapplied to the logic element.

Abstract translation: 本发明提供了在改变时钟频率时减少电路中的电流尖峰。 第一个频率被应用到时钟分配网络。 选择最终频率。 第一个频率通过时钟分配网络应用于逻辑元件。 保持信号被施加到逻辑元件。 时钟分配网络的时钟速率从第一个频率改变到最后的频率。 保持信号未应用于逻辑元件。

公开(公告)号：US20080272820A1

公开(公告)日：2008-11-06

申请号：US12132871

申请日：2008-06-04

Applicant: David William Boerstler ,  Eskinder Hailu ,  Mack Wayne Riley ,  Michael Fan Wang

Inventor： David William Boerstler ,  Eskinder Hailu ,  Mack Wayne Riley ,  Michael Fan Wang

IPC: H03K3/00

CPC classification number: H03K23/662 ,  G06F1/3203 ,  G06F1/324 ,  Y02D10/126

Abstract: A method, an apparatus, and a computer program are provided to reduce transient current swings during mode transitions. Traditionally, transient supply voltage fluctuations on a chip account for a large portion of the power supply. The number of series inductances and resistances are typically minimized, while adding large decoupling capacitances between the supply voltage and ground. However, situations may arise where reduction of series inductances and resistances cannot be accomplished. Therefore, to assist in controlling the transient current swings, reduction of clocking frequencies are performed in a controlled manner.

Abstract translation: 提供了一种方法，装置和计算机程序以减少模式转换期间的瞬态电流摆动。 传统上，芯片上的瞬态电源电压波动占大部分电源。 串联电感和电阻的数量通常最小化，同时在电源电压和地之间增加大的去耦电容。 然而，不能实现串联电感和电阻的降低的情况。 因此，为了帮助控制瞬态电流摆动，以受控的方式执行时钟频率的降低。

公开(公告)号：US20080052579A1

公开(公告)日：2008-02-28

申请号：US11463904

申请日：2006-08-11

Applicant: Mack Wayne Riley ,  Michael Fan Wang

Inventor： Mack Wayne Riley ,  Michael Fan Wang

IPC: G01R31/28

CPC classification number: G01R31/318575

Abstract: A system and method for advanced logic built-in self test with selection of scan channels is present. An LBIST controller loads scan patterns into a device's scan channels through sequential or interleaved loading techniques in order to minimize instantaneous power requirements. During interleave loading, the LBIST controller loads a scan bit into a first scan chain, then into a second scan chain, etc. until one bit is loaded into each scan chain. The LBIST controller then returns to load another scan bit into the first scan channel, then the second scan channel, etc. During sequential loading, the LBIST controller loads an entire scan pattern into a first scan chain (one bit per clock cycle). Once the first scan pattern is loaded, the LBIST controller proceeds to load subsequent scan patterns into corresponding scan chains on a one bit per scan channel per clock cycle basis.

Abstract translation: 存在具有选择扫描通道的高级逻辑内置自检的系统和方法。 LBIST控制器通过顺序或交错加载技术将扫描图案加载到设备的扫描通道中，以最小化瞬时功率需求。 在交错加载期间，LBIST控制器将扫描位加载到第一个扫描链中，然后加载到第二个扫描链等中，直到一个位加载到每个扫描链中。 LBIST控制器然后返回将另一个扫描位加载到第一个扫描通道，然后是第二个扫描通道等。在连续加载期间，LBIST控制器将整个扫描模式加载到第一个扫描链（每个时钟周期一个位）。 一旦加载了第一个扫描模式，LBIST控制器就会按照每个时钟周期的每个扫描通道一个位的速度将后续扫描模式加载到相应的扫描链中。

公开(公告)号：US09336105B2

公开(公告)日：2016-05-10

申请号：US12895102

申请日：2010-09-30

Applicant: Mack Wayne Riley

Inventor： Mack Wayne Riley

IPC: G01R31/28 ,  G06F11/22 ,  G06F11/27

CPC classification number: G06F11/2242 ,  G06F11/27

Abstract: Provided is an apparatus that includes a processor comprising a plurality of processing cores and a corresponding plurality of LBIST modules, each LBIST module corresponding to one of the plurality of processing cores; a MISR read out connection, comprising a compare value register, a plurality of MISR registers equal in number to the plurality of cores, each MISR register corresponding to one of the plurality of processing cores and a corresponding plurality of XOR logic gates, each XOR logic gate coupled to the compare value register and a corresponding one of the MISR registers and configured to signal whether or not the event the compare value register and the corresponding MISR register match and logic, stored and executed on the processor, for transmitting the signals generated by the plurality of XOR logic gates.

Abstract translation: 提供了一种装置，其包括：处理器，包括多个处理核和对应的多个LBIST模块，每个LBIST模块对应于所述多个处理核心中的一个; MISR读出连接，包括比较值寄存器，与多个核数相等的多个MISR寄存器，每个MISR寄存器对应于多个处理核中的一个和相应的多个异或逻辑门，每个XOR逻辑 栅极耦合到比较值寄存器和相应的一个MISR寄存器，并且被配置为用信号来表示比较值寄存器和对应的MISR寄存器的事件是否与在处理器上存储和执行的逻辑匹配和逻辑，用于发送由 多个异或逻辑门。

公开(公告)号：US07698608B2

公开(公告)日：2010-04-13

申请号：US11956458

申请日：2007-12-14

Applicant: Mack Wayne Riley

Inventor： Mack Wayne Riley

IPC: G11C29/00

CPC classification number: G11C29/44 ,  G11C29/72 ,  G11C29/789 ,  G11C29/802 ,  G11C2029/1208 ,  G11C2029/4402

Abstract: A mechanism is provided for using a single bank of electric fuses (eFuses) to successively store test data derived from multiple stages of testing are provided. To encode and store array redundancy data from each subsequent test in the same bank of eFuses, a latch on a scan chain is used that holds the programming information for each eFuse. This latch allows for programming only a portion of eFuses during each stage of testing. Moreover, the data programmed in the eFuses can be sensed and read as part of a scan chain. Thus, it can be easily determined what portions of the bank of eFuses have already been programmed by a previous stage of testing and where to start programming the next set of data into the bank of eFuses. As a result, the single bank of eFuses stores multiple sets of data from a plurality of test stages.

Abstract translation: 提供了一种使用单组电保险丝（eFuses）连续存储从多个测试阶段得到的测试数据的机制。 为了在同一组eFuses组中对每个后续测试中的阵列冗余数据进行编码和存储，使用扫描链上的锁存器来保存每个eFuse的编程信息。 该锁存器允许在每个测试阶段只编程一部分eFuses。 此外，eFuses中编程的数据可以作为扫描链的一部分进行检测和读取。 因此，可以很容易地确定电子货币银行的哪些部分已经由先前的测试阶段编程，以及在哪里开始将下一组数据编程到eFuses库中。 结果，单组eFuses存储来自多个测试阶段的多组数据。