公开(公告)号：US20240105259A1

公开(公告)日：2024-03-28

申请号：US18228621

申请日：2023-07-31

Applicant: MEDIATEK INC.

Inventor： Weinan Liao ,  Chi-Hao Hong

IPC: G11C11/418 ,  G11C11/419

CPC classification number: G11C11/418 ,  G11C11/419

Abstract: A pseudo multi-port memory includes a memory array, a row decoder circuit, a timing controller circuit, a sense amplifier circuit, and a write driver circuit. The timing controller circuit outputs a timing control signal to the row decoder circuit, wherein during one memory clock cycle, the row decoder circuit is controlled by the timing control signal to make a read wordline (RWL) signal have an enable pulse and a write wordline (WWL) signal have multiple enable pulses. During one memory clock cycle, the sense amplifier circuit performs read operations upon a selected memory cell when the selected RWL is enabled by the enable pulse and the selected WWL is enabled by at least one first enable pulse, and the write driver circuit performs a write operation upon the selected memory cell when the selected WWL is enabled by one second enable pulse.

公开(公告)号：US20240312515A1

公开(公告)日：2024-09-19

申请号：US18444776

申请日：2024-02-19

Applicant: MEDIATEK INC.

Inventor： Weinan Liao ,  Jiann-Tseng Huang

IPC: G11C11/419

CPC classification number: G11C11/419

Abstract: The present invention provides a memory device including a memory array, an IO circuitry and a control circuit. The IO circuitry is configured to access the memory array. The control circuit is configured to generate at least a global IO signal to the IO circuitry, to control operations of the IO circuitry, wherein the IO circuitry is supplied by a first supply voltage, the control circuit is supplied by at least a second supply voltage different from the first supply voltage.

公开(公告)号：US20240312514A1

公开(公告)日：2024-09-19

申请号：US18444754

申请日：2024-02-18

Applicant: MEDIATEK INC.

Inventor： Weinan Liao ,  Jiann-Tseng Huang

IPC: G11C11/419

CPC classification number: G11C11/419

Abstract: The present invention provides a memory device including a memory array, an IO circuitry and a control circuit. The IO circuitry includes a write buffer and a negative voltage provider. The write driver is configured to receive input data to drive bit lines of the memory array, and the negative voltage provider is configured to generate to generate a negative voltage to the write driver. The control circuit includes an NBL timing control circuit configured to generate an NBL enable signal to selectively enable the negative voltage provider. In addition, the memory device is supplied by a first supply voltage and a second supply voltage, a voltage level of the second supply voltage is higher than a voltage level of the first supply voltage, and the negative voltage provider and the NBL timing control circuit are supplied by the second supply voltage.