公开(公告)号：US20240312557A1

公开(公告)日：2024-09-19

申请号：US18443347

申请日：2024-02-16

Applicant: MEDIATEK INC.

Inventor： Che-Wei Chou ,  Ya-Ting Yang ,  Shu-Lin Lai ,  Chi-Kai Hsieh ,  Yi-Ping Kuo ,  Chi-Hao Hong ,  Jia-Jing Chen ,  Yi-Te Chiu ,  Jiann-Tseng Huang

IPC: G11C29/00 ,  G11C29/56

CPC classification number: G11C29/702 ,  G11C29/56008 ,  G11C29/56016

Abstract: A memory with built-in synchronous-write-through (SWT) redundancy includes a plurality of memory input/output (IO) arrays, a plurality of SWT circuits, and at least one spare SWT circuit. The at least one spare SWT circuit is used to replace at least one of the plurality of SWT circuits that is defective.

公开(公告)号：US20240312515A1

公开(公告)日：2024-09-19

申请号：US18444776

申请日：2024-02-19

Applicant: MEDIATEK INC.

Inventor： Weinan Liao ,  Jiann-Tseng Huang

IPC: G11C11/419

CPC classification number: G11C11/419

Abstract: The present invention provides a memory device including a memory array, an IO circuitry and a control circuit. The IO circuitry is configured to access the memory array. The control circuit is configured to generate at least a global IO signal to the IO circuitry, to control operations of the IO circuitry, wherein the IO circuitry is supplied by a first supply voltage, the control circuit is supplied by at least a second supply voltage different from the first supply voltage.

公开(公告)号：US20240312514A1

公开(公告)日：2024-09-19

申请号：US18444754

申请日：2024-02-18

Applicant: MEDIATEK INC.

Inventor： Weinan Liao ,  Jiann-Tseng Huang

IPC: G11C11/419

CPC classification number: G11C11/419

Abstract: The present invention provides a memory device including a memory array, an IO circuitry and a control circuit. The IO circuitry includes a write buffer and a negative voltage provider. The write driver is configured to receive input data to drive bit lines of the memory array, and the negative voltage provider is configured to generate to generate a negative voltage to the write driver. The control circuit includes an NBL timing control circuit configured to generate an NBL enable signal to selectively enable the negative voltage provider. In addition, the memory device is supplied by a first supply voltage and a second supply voltage, a voltage level of the second supply voltage is higher than a voltage level of the first supply voltage, and the negative voltage provider and the NBL timing control circuit are supplied by the second supply voltage.