公开(公告)号：US11082013B2

公开(公告)日：2021-08-03

申请号：US15975783

申请日：2018-05-10

Applicant: MEDIATEK INC.

Inventor： Ching-Shyang Maa ,  Chun-Hsien Peng ,  Hua-Lung Yang ,  I-No Liao ,  Chen-Jui Hsu ,  Jen-Yang Liu

IPC: H03F3/04 ,  H03F1/32 ,  H03F3/21 ,  H03F3/19 ,  H03F1/30 ,  H03F1/02 ,  H03F3/24

Abstract: A method of reducing memory effect of a power amplifier (PA), for a look-up table (LUT) based memory digital pre-distortion (DPD) circuit of an electronic device is disclosed. The method comprises generating a pre-distorted signal according to a LUT including parameters of an input signal amplitude and an input signal delay associated with a bandwidth of a signal inputted to the memory DPD circuit, and outputting the pre-distorted signal to the PA for improving the nonlinearity of the PA.

公开(公告)号：US20180331662A1

公开(公告)日：2018-11-15

申请号：US15975783

申请日：2018-05-10

Applicant: MEDIATEK INC.

Inventor： Ching-Shyang Maa ,  Chun-Hsien Peng ,  Hua-Lung Yang ,  I-No Liao ,  Chen-Jui Hsu ,  Jen-Yang Liu

IPC: H03F1/32 ,  H03F3/21 ,  H03F3/19 ,  H03F1/30

CPC classification number: H03F1/3258 ,  H03F1/30 ,  H03F3/19 ,  H03F3/21 ,  H03F2200/451 ,  H03F2200/468 ,  H03F2201/3209 ,  H03F2201/3224 ,  H03F2201/3233

Abstract: A method of reducing memory effect of a power amplifier (PA), for a look-up table (LUT) based memory digital pre-distortion (DPD) circuit of an electronic device is disclosed. The method comprises generating a pre-distorted signal according to a LUT including parameters of an input signal amplitude and an input signal delay associated with a bandwidth of a signal inputted to the memory DPD circuit, and outputting the pre-distorted signal to the PA for improving the nonlinearity of the PA.

公开(公告)号：US09525500B2

公开(公告)日：2016-12-20

申请号：US14953673

申请日：2015-11-30

Applicant: MediaTek Inc.

Inventor： Jen-Yang Liu ,  I-Cheng Tsai ,  Hsueh-Wei Chiu ,  Yuan-Hwui Chung ,  Chun-Hsien Peng

IPC: H04B17/00 ,  H04B17/29

CPC classification number: H04B17/29 ,  H04B17/0085

Abstract: A test/calibration system includes a device under test (DUT) and a calibrated device. The calibrated device is coupled to the DUT, transmits or receives a test signal to or from the DUT in response to a control signal for a test item to test, measure or calibrate functioning or performance of an internal component of the DUT.

Abstract translation: 测试/校准系统包括被测设备（DUT）和校准设备。 校准的设备耦合到DUT，响应于用于测试，测量或校准DUT的内部部件的功能或性能的测试项目的控制信号，向DUT发送或接收来自DUT的测试信号。