公开(公告)号：US3372245A

公开(公告)日：1968-03-05

申请号：US33867964

申请日：1964-01-20

Applicant: MATSUSHITA ELECTRIC IND CO LTD

Inventor： YOSHIDA TOMIO ,  RIKO YASUHIRO

IPC: H04R3/00 ,  H04R19/02

CPC classification number: H04R3/002 ,  H04R19/02

公开(公告)号：US3638196A

公开(公告)日：1972-01-25

申请号：US3638196D

申请日：1970-07-13

Applicant: MATSUSHITA ELECTRIC IND CO LTD

Inventor： NISHIYAMA AKIRA ,  YOSHINO HIROKAZU ,  YOSHIDA TOMIO ,  YAMAGUCHI TETSUO

IPC: G06K9/62 ,  G06F7/02 ,  G06F15/18

CPC classification number: G06F7/023

Abstract: A learning machine in which threshold values corresponding to the desired output conditions and having a dead zone therebetween are used during the learning process for the discrimination of the output from a memory storing a plurality of standard pattern information, and this discriminating faculty is utilized for the discrimination of input pattern information with respect to a single threshold value having no dead zone. Thus, the precision of discrimination can be remarkably improved due to the fact that the threshold values having a dead zone are used during the learning process, and the learning can be digitally and automatically carried out.

Abstract translation: 一种在学习过程中使用对应于期望输出条件并且具有死区的阈值的学习机器，用于区分来自存储多个标准模式信息的存储器的输出，并且该鉴别教师被用于 相对于没有死区的单个阈值的输入模式信息的区分。 因此，由于在学习过程中使用具有死区的阈值的事实，因此可以显着提高鉴别的精度，并且可以数字和自动地进行学习。

公开(公告)号：US3646329A

公开(公告)日：1972-02-29

申请号：US3646329D

申请日：1969-11-13

Applicant: MATSUSHITA ELECTRIC IND CO LTD

Inventor： YOSHINO HIROKAZU ,  YOSHIDA TOMIO

IPC: G06K9/66 ,  G06F7/02 ,  G06F15/18 ,  G06N3/04 ,  G06N99/00 ,  H03K19/00 ,  G05B13/02

CPC classification number: G06F7/023

Abstract: An adaptive logic circuit which is a basic component circuit of a learning machine. A voltage divider comprising a variety of parallel resistances and a common resistance connected in series thereto gives weighting constants one of which is to be selected by applying outputs of respective stages of a shift register to the gates of MOS field effect transistors connected between the respective resistances and the common resistance. The MOS field effect transistor whose control terminal is supplied with an input signal becomes conductive thereby providing a threshold function. This circuit can be formed entirely of solid state elements, enabling the electronic setting of weights so that the learning processes can be performed at very high speed.

Abstract translation: 自适应逻辑电路是学习机的基本组成电路。 包括各种并联电阻和共同电阻串联连接的分压器给出加权常数，通过将移位寄存器的各个级的输出施加到连接在各个电阻之间的MOS场效应晶体管的栅极来选择其中之一 和共同的阻力。 其控制端被提供输入信号的MOS场效应晶体管导通，从而提供阈值函数。 该电路可以完全由固态元件形成，使得能够电子设置权重，使得可以以非常高的速度执行学习过程。

公开(公告)号：US3660767A

公开(公告)日：1972-05-02

申请号：US3660767D

申请日：1969-12-18

Applicant: MATSUSHITA ELECTRIC IND CO LTD

Inventor： YOSHINO HIROKAZU ,  YOSHIDA TOMIO

IPC: H03B19/00

CPC classification number: H03B19/00

Abstract: A frequency divider wherein the pulse input having been delayed by a predetermined time interval is impressed upon a plurality of cascade connected flip-flops, and the output from each of the flip-flops is fed to an AND gate to which is also fed the input which has not passed through the delay circuit to produce a resultant AND output to be fed back to each of the required flipflops, thereby increasing the upper limit of the frequency to be divided and practically eliminating the danger of a malfunction in the system.

Abstract translation: 已经延迟预定时间间隔的脉冲输入的分频器被施加到多个级联连接的触发器上，并且每个触发器的输出被馈送到也被馈送到输入端的“与”门 其没有通过延迟电路以产生所得到的AND输出以反馈到每个所需的触发器，从而增加了要被分割的频率的上限，实际上消除了系统故障的危险。

公开(公告)号：US3602888A

公开(公告)日：1971-08-31

申请号：US3602888D

申请日：1968-12-09

Applicant: MATSUSHITA ELECTRIC IND CO LTD

Inventor： NISHIYAMA AKIRA ,  YOSHINO HIROKAZU ,  YOSHIDA TOMIO ,  YAMAGUCHI TETSUO

IPC: G06F7/02 ,  G06F15/18

CPC classification number: G06F7/023

Abstract: A learning device having a plurality of magnetic cores which serve as multistage level weight memory elements. In the device, the product of an input and a corresponding weight is delivered from the magnetic core in the form of a digital output, and the sum of digital outputs is compared with a threshold value in a decision circuit to derive an error signal so that the weight carried by each magnetic core can fully automatically be corrected until the actual output coincides with an expected output.

公开(公告)号：US3592969A

公开(公告)日：1971-07-13

申请号：US3592969D

申请日：1969-07-22

Applicant: MATSUSHITA ELECTRIC IND CO LTD

Inventor： YOSHINO HIROKAZU ,  YOSHIDA TOMIO

IPC: G10L15/065 ,  G10L15/07 ,  G10L1/00

CPC classification number: G10L15/065 ,  G10L15/07

Abstract: One of the greatest problems tending to occur in an attempt to effect speech recognition with a speech recognition apparatus is that individual difference is present in the speech frequency distribution. Obviously, the apparatus fails to recognize a speech correctly which can naturally be recognized by the human being, if there is such individual difference. This specification discloses an apparatus wherein individual difference is eliminated from the frequency to time pattern to normalize such pattern in an attempt to effect speech recognition, thereby making it possible to achieve accurate speech recognition.