-
公开(公告)号：US10230354B2
公开(公告)日：2019-03-12
申请号：US15315559
申请日：2015-07-29
发明人： Robert John Leedham , Mark Snook
IPC分类号： H03K3/011 , H03K17/10 , H03K17/16 , H03K17/082 , H03K17/567
摘要： A method for voltage balancing series-connected power switching devices (IGBTs) each connected in parallel with a respective diverter having controllable impedance to controllably conduct current diverted from the associated power switching device, the method comprising the step of controlling each diverter to follow a series of at least two successively higher impedance states during an OFF period of the power switching devices. The series of impedance states for each diverter comprises a first impedance and then a second, higher impedance, the first impedance occurring in response to an indication of a start of the OFF period. The first impedance state preferably occurs during a tail current of the power switching device in parallel with the respective diverter and the second or later impedance state during a leakage current of that power switching device.
-
公开(公告)号：US10069431B2
公开(公告)日：2018-09-04
申请号：US14894538
申请日：2014-06-17
发明人： Robert John Leedham , Matteo Vit , Stephen Parker , Ivan Cronin
摘要： The invention generally relates to power converters, and more particularly to a communications method for controlling at least one power switching device of a power converter, a communications system for a power converter, and a power converter comprising the communications system. For example there is provided a communications method for controlling at least one power switching device of a power converter, the method comprising: inputting a signal to a transmit end of a communications link; inputting data to the transmit end of the communications link; determining whether the signal comprises a transition; when said determination indicates that the signal comprises a transition, transmitting the signal comprising the transition into a communications channel of the communications link, wherein the transmitted signal is delayed by a predetermined time delay relative to the inputted signal, said predetermined time delay to allow said determining; transmitting the data on the communications channel, wherein when said determination indicates that the signal comprises a transition the transmitting the data is delayed until after said transmitting the signal; and if the signal has been transmitted, receiving the transmitted signal at the receive end of the communications link and controlling at least one said power switching device dependent on said received signal.
-
公开(公告)号：US09762114B2
公开(公告)日：2017-09-12
申请号：US14894583
申请日：2014-06-17
发明人： Robin Lyle , Mark Snook , Robert John Leedham
IPC分类号： G05F1/12 , G05B24/02 , H02J1/00 , H02J3/12 , G05B11/01 , H02M5/42 , H02M7/68 , H02M3/24 , H02M7/44 , H02M7/538 , H02M1/088 , H03K17/12 , H03K17/28
CPC分类号： H02M1/088 , H03K17/127 , H03K17/28
摘要： The invention generally relates to methods and circuits for controlling switching of parallel coupled power semiconductor switching devices (3), for example for use in a power converter. In an example, there is provided a circuit for controlling switching of parallel coupled power semiconductor switching devices (3), the circuit comprising: a plurality of drive modules (2), each said module for controlling a said power semiconductor switching device (3); control circuitry to transmit switch command signals to the modules, each said switch command signal to trigger a said drive module to control a said power semiconductor switching device to switch state; and voltage isolation between the drive modules and the control circuitry, wherein each said drive module for controlling a said device comprises: timing circuitry (22) to compare a switching delay of the device and a reference delay, wherein said switching delay is a time interval between detecting a said switching command signal at the drive module and switching of the device in accordance with the detected switching command signal; and delay circuitry (21) to provide a controllable delay to delay a said triggering by a said switching command signal received at the module subsequent to the detected switching command signal, the delay circuitry configured to control the controllable delay according to a result of said comparison of said switching delay of the device, to thereby reduce a time difference between the reference delay and a said switching delay of the device switching in accordance with the subsequent switching command signal.
-
公开(公告)号：US10199916B2
公开(公告)日：2019-02-05
申请号：US15515982
申请日：2015-11-09
发明人： Mark Snook , Robert John Leedham , Robin Lyle
IPC分类号： H02M1/08 , H03K17/04 , H03K17/042 , H03K17/06 , H03K17/082 , H03K17/16 , H03K5/08 , H02M7/5387 , H02M1/00
摘要： A power switch driver for driving a control terminal of a power switch to drive a load, the power switch driver having a negative feedback circuit to control current delivered to the control terminal. The negative feedback circuit has a current output circuit having a current source and a current sink and serving for providing the current of the control terminal and configured to receive an output current control signal to control a magnitude of the current provided by the current output circuit, a terminal voltage input circuit for receiving a voltage from the control terminal and to output an indication of the voltage, an amplifier coupled to the terminal voltage input circuit for amplifying the terminal voltage indication to generate an amplifier output, and a reference voltage input circuit for receiving a reference voltage, having at least one resistor, and coupled to a charge supply input of the amplifier.
-
-
-
搜索结果
4 条记录 (耗时 0.012 秒)
