Computer architecture with disaggregated memory and high-bandwidth communication interconnects

    公开(公告)号:US12099724B2

    公开(公告)日:2024-09-24

    申请号:US18149013

    申请日:2022-12-30

    CPC classification number: G06F3/0613 G06F3/0629 G06F3/0659 G06F3/0673

    Abstract: Conventional high performance computer connections are electron-based systems, which require the memory packages to be as close as mechanically possible to the computation engine. Low power and high bandwidth communication, e.g. photonic, links can drastically change the architecture of high-performance computers by eliminating the bottlenecks in communication. A computer system comprises: a plurality of memory aggregation devices configured to retrieve data from and store data in a plurality of random access memory modules forming a unified contiguous memory address space disaggregated from a central processing unit; a plurality of computational devices configured for simultaneously launching a plurality of data signals including memory read and/or write requests for the data to the plurality of memory aggregation devices; and a plurality of communication links coupling each of the plurality of memory aggregation devices to each of the plurality of computational devices for transferring the data therebetween.

Patent Agency Ranking