COMPUTER SYSTEM AND METHOD FOR DATA ACCESS
    1.
    发明公开

    公开(公告)号:US20240078046A1

    公开(公告)日:2024-03-07

    申请号:US18462096

    申请日:2023-09-06

    CPC classification number: G06F3/0659 G06F3/0611 G06F3/0683

    Abstract: A computer system comprises one or more processing units and a plurality of memory locations interconnected by a plurality of data links, each processing unit comprising a data request engine and a processor. A method for accessing data in memory of the computer system, includes: receiving a data access job at a first data request engine specifying data to be accessed; and generating a plurality of memory access requests to request the plurality of data partitions needed to fulfill the data access job. The plurality of memory access requests are then delivered to the plurality of memory locations, and the plurality of data partitions are copied or moved from the plurality of memory locations to the first processing unit via the data links. The data access job specifies a plurality of data partitions of a source data structure distributed over the plurality of memory locations of the computer system. One purpose of this computer system is to accelerate the accessing of the rows or vectors in an embedding table for machine learning.

    Computer architecture with disaggregated memory and high-bandwidth communication interconnects

    公开(公告)号:US12099724B2

    公开(公告)日:2024-09-24

    申请号:US18149013

    申请日:2022-12-30

    CPC classification number: G06F3/0613 G06F3/0629 G06F3/0659 G06F3/0673

    Abstract: Conventional high performance computer connections are electron-based systems, which require the memory packages to be as close as mechanically possible to the computation engine. Low power and high bandwidth communication, e.g. photonic, links can drastically change the architecture of high-performance computers by eliminating the bottlenecks in communication. A computer system comprises: a plurality of memory aggregation devices configured to retrieve data from and store data in a plurality of random access memory modules forming a unified contiguous memory address space disaggregated from a central processing unit; a plurality of computational devices configured for simultaneously launching a plurality of data signals including memory read and/or write requests for the data to the plurality of memory aggregation devices; and a plurality of communication links coupling each of the plurality of memory aggregation devices to each of the plurality of computational devices for transferring the data therebetween.

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