公开(公告)号：US08878304B2

公开(公告)日：2014-11-04

申请号：US13358242

申请日：2012-01-25

申请人： Li-Wen Fang ,  Chih-Hao Yang ,  An-Tung Chen

发明人： Li-Wen Fang ,  Chih-Hao Yang ,  An-Tung Chen

IPC分类号： H01L27/06 ,  G11C29/00 ,  H01L27/02

CPC分类号： G11C29/785 ,  H01L27/0255 ,  H01L27/0617

摘要： The present invention discloses a fuse circuit for final test trimming of an integrated circuit (IC) chip. The fuse circuit includes at least one electrical fuse, at least one control switch corresponding to the electrical fuse, and a resistant device. The electrical fuse is connected with the control switch in series between a predetermined pin and a grounding pin. The control switch receives a control signal to determine whether a predetermined current flows through the corresponding electrical fuse and breaks the electrical fuse. The resistant device is coupled between a bulk terminal and a source terminal to increase a resistance of a parasitic channel, such that an electrostatic discharge (ESD) protection is enhanced, and errors of final test trimming of an IC chip are avoided.

摘要翻译： 本发明公开了一种用于集成电路（IC）芯片的最终测试修整的熔丝电路。 熔断器电路包括至少一个电熔丝，对应于电熔丝的至少一个控制开关和一个电阻装置。 电保险丝与控制开关串联连接在预定的引脚和接地引脚之间。 控制开关接收控制信号以确定预定电流是否流过相应的电熔丝并断开电熔丝。 电阻器件耦合在体端子和源极端子之间以增加寄生沟道的电阻，从而增强了静电放电（ESD）保护，并且避免了IC芯片的最终测试修整的误差。

公开(公告)号：US20090066399A1

公开(公告)日：2009-03-12

申请号：US12230953

申请日：2008-09-09

申请人： An-Tung Chen ,  Li-Wen Fang ,  Hung-Der Su

发明人： An-Tung Chen ,  Li-Wen Fang ,  Hung-Der Su

IPC分类号： H03L5/00

CPC分类号： H03K3/012 ,  H03K3/35613

摘要： A level shift circuit includes an input stage and an output stage coupled to each other by two nodes. The input stage changes the voltages on the nodes according to an input signal, and the output stage determines an output signal according to the voltages on the two nodes. In a transition state, the input stage provides a large current to charge or discharge the first node or the second node so as to quickly change the voltage thereon. In a steady state, the input stage lowers the current so as to reduce power consumption.

摘要翻译： 电平移位电路包括通过两个节点彼此耦合的输入级和输出级。 输入级根据输入信号改变节点上的电压，输出级根据两个节点上的电压来确定输出信号。 在过渡状态下，输入级提供大电流以对第一节点或第二节点进行充电或放电，以便快速地改变其上的电压。 在稳定状态下，输入级降低电流，从而降低功耗。

公开(公告)号：US07839197B2

公开(公告)日：2010-11-23

申请号：US12230953

申请日：2008-09-09

申请人： An-Tung Chen ,  Li-Wen Fang ,  Hung-Der Su

发明人： An-Tung Chen ,  Li-Wen Fang ,  Hung-Der Su

IPC分类号： H03L5/00

CPC分类号： H03K3/012 ,  H03K3/35613

摘要： A level shift circuit includes an input stage and an output stage coupled to each other by two nodes. The input stage changes the voltages on the nodes according to an input signal, and the output stage determines an output signal according to the voltages on the two nodes. In a transition state, the input stage provides a large current to charge or discharge the first node or the second node so as to quickly change the voltage thereon. In a steady state, the input stage lowers the current so as to reduce power consumption.

摘要翻译： 电平移位电路包括由两个节点彼此耦合的输入级和输出级。 输入级根据输入信号改变节点上的电压，输出级根据两个节点上的电压来确定输出信号。 在过渡状态下，输入级提供大电流以对第一节点或第二节点进行充电或放电，以便快速地改变其上的电压。 在稳定状态下，输入级降低电流，从而降低功耗。

公开(公告)号：US20110018514A1

公开(公告)日：2011-01-27

申请号：US12658692

申请日：2010-02-12

申请人： An-Tung Chen ,  Li-Wen Fang

发明人： An-Tung Chen ,  Li-Wen Fang

IPC分类号： G05F1/10

CPC分类号： H02M3/1588 ,  H02M2001/0032 ,  H02M2001/0048 ,  Y02B70/1466 ,  Y02B70/1491 ,  Y02B70/16

摘要： The present invention discloses a dual-mode buck switching regulator, comprising: a first power transistor having an end coupled to an input voltage and another end coupled to a common node; an inductor having an end coupled to the common node and another end coupled to the input voltage; a second power transistor having an end coupled to ground; a diode having an end coupled to ground; and a control circuit generating a first and a second switch control signals for controlling operations of the first and the second power transistors according to a feedback signal, and generating a mode selection signal according a mode control signal to select a synchronous or an asynchronous mode, wherein the second power transistor has another end which is coupled to the common node in the synchronous mode, and the diode has another end which is coupled to the common node in the asynchronous mode, and in the asynchronous mode: the another end of the second power transistor is not coupled to the common mode, or the second power transistor maintains off. The present invention also relates to a control circuit of the dual-mode buck switching regulator.

摘要翻译： 本发明公开了一种双模降压开关调节器，包括：第一功率晶体管，其一端耦合到输入电压，另一端耦合到公共节点; 电感器，其端部耦合到公共节点，另一端耦合到输入电压; 第二功率晶体管，其端部耦合到地; 二极管，其一端与地耦合; 以及控制电路，根据反馈信号产生用于控制第一和第二功率晶体管的操作的第一和第二开关控制信号，并且根据模式控制信号产生模式选择信号以选择同步或异步模式， 其中所述第二功率晶体管具有以同步模式耦合到所述公共节点的另一端，并且所述二极管具有以所述异步模式耦合到所述公共节点并且处于所述异步模式的另一端：所述第二功率晶体管的另一端 功率晶体管不耦合到共模，或者第二功率晶体管保持断开。 本发明还涉及双模降压开关调节器的控制电路。

公开(公告)号：US20120019219A1

公开(公告)日：2012-01-26

申请号：US13135990

申请日：2011-07-20

申请人： Li-Wen Fang ,  Ting-Jung Tai ,  Chih-Hao Yang

发明人： Li-Wen Fang ,  Ting-Jung Tai ,  Chih-Hao Yang

IPC分类号： G05F1/10

CPC分类号： H02M3/156 ,  H02M2001/0035 ,  Y02B70/16

摘要： The present invention discloses a constant on-time switching regulator, a control method therefor, and an on-time calculation circuit for calculating an on-time period of a constant on-time switching regulator. The on-time calculation circuit calculates on-time according to practical conditions. It includes: a driver gate receiving a gate signal of a power switch in a switching regulator, the driver gate operating between high and low levels of a first reference voltage and ground; a low pass filter receiving an output from the driver gate and generating a second reference voltage, a ratio between the second reference voltage and the first reference voltage being substantially the same as a duty ratio of the gate signal; and an on-time generator comparing the second reference voltage with a ramp signal to determine an on-time of the power switch.

公开(公告)号：US08669747B2

公开(公告)日：2014-03-11

申请号：US13135990

申请日：2011-07-20

申请人： Li-Wen Fang ,  Ting-Jung Tai ,  Chih-Hao Yang

发明人： Li-Wen Fang ,  Ting-Jung Tai ,  Chih-Hao Yang

IPC分类号： G05F1/10

CPC分类号： H02M3/156 ,  H02M2001/0035 ,  Y02B70/16

摘要： The present invention discloses a constant on-time switching regulator, a control method therefor, and an on-time calculation circuit for calculating an on-time period of a constant on-time switching regulator. The on-time calculation circuit calculates on-time according to practical conditions. It includes: a driver gate receiving a gate signal of a power switch in a switching regulator, the driver gate operating between high and low levels of a first reference voltage and ground; a low pass filter receiving an output from the driver gate and generating a second reference voltage, a ratio between the second reference voltage and the first reference voltage being substantially the same as a duty ratio of the gate signal; and an on-time generator comparing the second reference voltage with a ramp signal to determine an on-time of the power switch.

摘要翻译： 本发明公开了一种恒定导通时间开关调节器及其控制方法，以及用于计算恒定导通时间开关调节器的导通时间周期的接通时间计算电路。 导通时间计算电路根据实际条件准时计算。 它包括：驱动器门接收开关调节器中的电源开关的门信号，驱动器门在第一参考电压和地的高电平和低电平之间工作; 接收来自所述驱动器门的输出并产生第二参考电压的低通滤波器，所述第二参考电压与所述第一参考电压之间的比率基本上与所述栅极信号的占空比相同; 以及导通时间发生器，将所述第二参考电压与斜坡信号进行比较，以确定所述电源开关的接通时间。

公开(公告)号：US08531166B2

公开(公告)日：2013-09-10

申请号：US13066595

申请日：2011-04-19

申请人： Li-Wen Fang ,  Ting-Jung Tai ,  Chih-Hao Yang

发明人： Li-Wen Fang ,  Ting-Jung Tai ,  Chih-Hao Yang

IPC分类号： G05F1/40

CPC分类号： H02M3/156

摘要： The present invention discloses a constant on-time switching regulator, a control method therefor, and an on-time calculation circuit for calculating an on-time period of a constant on-time switching regulator. The on-time calculation circuit calculates on-time according to practical conditions. It includes: a driver gate receiving a gate signal of a power switch in a switching regulator, the driver gate operating between high and low levels of a first reference voltage and ground; a low pass filter receiving an output from the driver gate and generating a second reference voltage, a ratio between the second reference voltage and the first reference voltage being substantially the same as a duty ratio of the gate signal; and an on-time generator comparing the second reference voltage with a ramp signal to determine an on-time of the power switch.

摘要翻译： 本发明公开了一种恒定导通时间开关调节器及其控制方法，以及用于计算恒定导通时间开关调节器的导通时间周期的接通时间计算电路。 导通时间计算电路根据实际条件准时计算。 它包括：驱动器门接收开关调节器中的电源开关的门信号，驱动器门在第一参考电压和地的高电平和低电平之间工作; 接收来自所述驱动器门的输出并产生第二参考电压的低通滤波器，所述第二参考电压与所述第一参考电压之间的比率基本上与所述栅极信号的占空比相同; 以及导通时间发生器，将所述第二参考电压与斜坡信号进行比较，以确定所述电源开关的接通时间。

公开(公告)号：US20120019218A1

公开(公告)日：2012-01-26

申请号：US13066595

申请日：2011-04-19

申请人： Li-Wen Fang ,  Ting-Jung Tai ,  Chih-Hao Yang

发明人： Li-Wen Fang ,  Ting-Jung Tai ,  Chih-Hao Yang

IPC分类号： G05F1/10

CPC分类号： H02M3/156

摘要： The present invention discloses a constant on-time switching regulator, a control method therefor, and an on-time calculation circuit for calculating an on-time period of a constant on-time switching regulator. The on-time calculation circuit calculates on-time according to practical conditions. It includes: a driver gate receiving a gate signal of a power switch in a switching regulator, the driver gate operating between high and low levels of a first reference voltage and ground; a low pass filter receiving an output from the driver gate and generating a second reference voltage, a ratio between the second reference voltage and the first reference voltage being substantially the same as a duty ratio of the gate signal; and an on-time generator comparing the second reference voltage with a ramp signal to determine an on-time of the power switch.

摘要翻译： 本发明公开了一种恒定导通时间开关调节器及其控制方法，以及用于计算恒定导通时间开关调节器的导通时间周期的接通时间计算电路。 导通时间计算电路根据实际条件准时计算。 它包括：驱动器门接收开关调节器中的电源开关的门信号，驱动器门在第一参考电压和地的高电平和低电平之间工作; 接收来自所述驱动器门的输出并产生第二参考电压的低通滤波器，所述第二参考电压与所述第一参考电压之间的比率基本上与所述栅极信号的占空比相同; 以及导通时间发生器，将所述第二参考电压与斜坡信号进行比较，以确定所述电源开关的接通时间。