公开(公告)号：US12002402B2

公开(公告)日：2024-06-04

申请号：US18084298

申请日：2022-12-19

申请人： LX Semicon Co., Ltd.

发明人： Gi Baek Choi ,  Jong Hwi Park ,  Yong Jung Kwon ,  Jung Bae Yun

IPC分类号： G09G3/20

CPC分类号： G09G3/2007 ,  G09G2310/027 ,  G09G2310/0297 ,  G09G2310/08 ,  G09G2320/02

摘要： An embodiment provides a latch circuit which outputs, to a digital analog converter (DAC), a digital signal including grayscale data, the latch circuit including a first latch configured to store the digital signal and a second latch configured to output the digital signal by controlling first timing at which a level of a first signal included in the digital signal becomes an enable level, based on a center grayscale. The grayscale data includes first grayscale data and second grayscale data.

公开(公告)号：US11862124B2

公开(公告)日：2024-01-02

申请号：US17779508

申请日：2020-11-13

申请人： LX Semicon Co., Ltd.

发明人： Ho Sung Hong ,  Gi Baek Choi ,  Sang Min Lee ,  Jung Bae Yun

IPC分类号： G09G5/00

CPC分类号： G09G5/006 ,  G09G2310/0275 ,  G09G2320/0247 ,  G09G2330/12 ,  G09G2370/08 ,  G09G2370/14

摘要： The present disclosure relates to a data transmission and reception method of a data driving device and a data processing device as well as a data transmission and reception system, and more particularly, to a method and a system in which the data driving device receives an initial configuration value from the data processing device, stores the initial configuration value as a configuration restoration value, and rapidly restore an environment for a high-speed communication by using the stored configuration restoration value when a link between the data processing device and the data driving device is lost so as to reduce a time for restoration.

公开(公告)号：US11935472B2

公开(公告)日：2024-03-19

申请号：US17764932

申请日：2020-09-28

申请人： LX Semicon Co., Ltd.

发明人： Seung Hwan Ji ,  Sang Min Lee ,  Gi Baek Choi ,  Jung Bae Yun

IPC分类号： G09G3/3233 ,  G09G3/3291

CPC分类号： G09G3/3233 ,  G09G3/3291 ,  G09G2310/0291 ,  G09G2320/0295 ,  G09G2330/12

摘要： The present disclosure relates to a pixel sensing circuit which extends an operation section of an integrator by using an additional signal and allows securing a time required for a stable output of a sensing voltage.

公开(公告)号：US11749167B2

公开(公告)日：2023-09-05

申请号：US17550664

申请日：2021-12-14

申请人： LX SEMICON CO., LTD.

发明人： Jong Hwi Park ,  Gi Baek Choi ,  Yong Jung Kwon ,  Jung Bae Yun

IPC分类号： G09G3/20

CPC分类号： G09G3/2092 ,  G09G2310/0275 ,  G09G2310/061 ,  G09G2310/08

摘要： The present disclosure relates to a data drive circuit capable of increasing clock and data recovery stability by generating a clock synchronized with input data, a clock recovery method thereof, and a display drive device having the same, and the data drive circuit according to an aspect includes a receiver including a clock and data recovery part configured to recover a test data pattern from input data using an internal clock, and a data comparator configured to compare the recovered test data pattern with a predetermined reference data pattern to generate a control signal according to a degree of asynchronicity between the recovered test data pattern and the reference data pattern, wherein the clock and data recovery part recovers a clock synchronized with the input data according to the control signal, and recovers control information and image data from the input data using the recovered clock.