公开(公告)号：US11645981B2

公开(公告)日：2023-05-09

申请号：US17860085

申请日：2022-07-07

申请人： LG Display Co., Ltd.

发明人： Seok Noh ,  Ki Min Son

IPC分类号： G09G3/3266 ,  G09G3/3233

CPC分类号： G09G3/3266 ,  G09G3/3233 ,  G09G2300/0819 ,  G09G2300/0842 ,  G09G2300/0861 ,  G09G2310/027 ,  G09G2310/0291 ,  G09G2310/0297 ,  G09G2310/08 ,  G09G2320/0673

摘要： Disclosed are a gate driver and a display panel including the same. The gate driver according to an embodiment includes a plurality of signal transfer units cascade-connected via a carry line to which a carry signal is applied from a previous signal transfer unit, and an nth (n is a positive integer) signal transfer unit includes a first output unit configured to output a first gate signal to a first output node according to a voltage of a first control node configured to pull up an output voltage and a second control node configured to pull down the output voltage; and a second output unit configured to output a second gate signal in which a phase of the first gate signal is reversed to a second output node, wherein the second output unit may include a first pull-up transistor configured to output a high potential voltage to the second output node according to a voltage of a second control node of an (n-i)th (i is a positive integer less than n) signal transfer unit; and a second pull-down transistor configured to output a first low potential voltage to the second output node according to a voltage of a first control node of an (n+j)th (j is a natural number greater than n) signal transfer unit.

公开(公告)号：US10546539B2

公开(公告)日：2020-01-28

申请号：US16116551

申请日：2018-08-29

申请人： LG Display Co., Ltd.

发明人： Kyung-Min Kim ,  In-Hyo Han ,  Seok Noh

IPC分类号： G09G3/30 ,  G09G3/3266 ,  G09G3/3291 ,  H01L27/32

摘要： Disclosed herein is an organic light emitting diode (OLED) display device including an OLED display panel including a non-active area and an active area, having a plurality of gate lines and a plurality of data lines disposed in the active area, and having a plurality of subpixels arranged at intersections between the gate lines and the data lines in a matrix, a gate driver disposed in the non-active area of the OLED display panel to supply a scan pulse to the plurality of gate lines, and a bootstrap capacitor for preventing output loss of the scan pulses of the gate driver in the active area of the OLED display panel.

公开(公告)号：US11887536B2

公开(公告)日：2024-01-30

申请号：US17859940

申请日：2022-07-07

申请人： LG Display Co., Ltd.

发明人： Ki Min Son ,  Chang Hee Kim ,  Seok Noh

IPC分类号： G09G3/3233 ,  G09G3/3266

CPC分类号： G09G3/3233 ,  G09G3/3266 ,  G09G2300/0819 ,  G09G2300/0852 ,  G09G2320/0233 ,  G09G2320/0247 ,  G09G2330/021

摘要： A pixel circuit comprises a first switch element comprising a first electrode to which an initialization voltage is applied, a gate electrode to which a initialization pulse is applied, and a second electrode connected to a second node; a second switch element comprising a first electrode connected to a third node or a fourth node, a gate electrode to which a sensing pulse is applied, and a second electrode to which a reference voltage is applied; a third switch element comprising a first electrode to which a data voltage is applied, a gate electrode to which a scan pulse is applied, and a second electrode connected to the second node; and a fourth switch element comprising a first electrode connected to the third node, a gate electrode to which a first emission control pulse is applied, and a second electrode connected to the fourth node.

公开(公告)号：US10783820B2

公开(公告)日：2020-09-22

申请号：US16136683

申请日：2018-09-20

申请人： LG Display Co., Ltd.

发明人： Seok Noh ,  Hae-Jin Park ,  Ki-Min Son

IPC分类号： G09G3/36 ,  G09G3/20 ,  H03K17/687 ,  G09G3/3266 ,  G11C19/28 ,  H03K17/16

摘要： Disclosed herein are a gate driver capable of implementing a narrow bezel by deleting dummy gate-in-panels (GIPs) and a flat panel display device including the same. The gate driver includes gate-in-panels (GIPs) equal in number to a plurality of gate lines in order to sequentially supply scan pulses to the plurality of gate lines. A k-th GIP is enabled by a carry pulse from a GIP of a (k−a)-th stage and is disabled by a carry pulse output from a GIP of a (k+b)-th stage (a and b are natural numbers), first a GIPs are enabled by a gate start signal output from a timing controller, and last b GIPs are disabled by a reset signal output from the timing controller.

公开(公告)号：US10170053B2

公开(公告)日：2019-01-01

申请号：US15391188

申请日：2016-12-27

申请人： LG DISPLAY CO., LTD.

发明人： Seok Noh ,  InHyo Han

IPC分类号： G09G3/3266 ,  G09G3/3233 ,  G09G3/36

摘要： A gate driving module and a gate-in-panel comprising a first pull-up TFT having a terminal connected to a gate driving signal generator and another terminal connected to an end of a first gate line, a first pull-down TFT having a terminal connected to the end of the first gate line and another terminal connected to a low-level voltage terminal, and a second pull-up TFT having a terminal connected to the gate driving signal generator and another terminal connected to another end opposite to the end of the first gate line, wherein the first pull-down TFT is turned off when the first pull-up TFT and the second pull-up TFT are turned on, and the first pull-down TFT is turned on when the first pull-up TFT and the second pull-up TFT are turned off.

公开(公告)号：US12087232B2

公开(公告)日：2024-09-10

申请号：US18471129

申请日：2023-09-20

申请人： LG Display Co., Ltd.

发明人： Seok Noh ,  Ki Min Son

IPC分类号： G09G3/3266 ,  G09G3/32 ,  G09G3/3291

CPC分类号： G09G3/3266 ,  G09G3/32 ,  G09G3/3291 ,  G09G2310/0267 ,  G09G2310/0275 ,  G09G2310/0286

摘要： A gate driver according to an embodiment and a display device using the same are disclosed. The gate driver includes a plurality of signal transmitters, wherein an nth signal transmitter includes, a (1-1)th output circuit configured to output a carry signal to a first output node according to a voltage of a first control node and a voltage of a second control node, a (1-2)th output circuit configured to output a boosting signal to a second output node according to a voltage of the first control node and a voltage of the second control node, wherein the (1-2)th output circuit includes a pull-up transistor configured to apply a gate high voltage to the first output node, a pull-down transistor configured to apply a gate low voltage to the first output node, and a first capacitor connected between a gate of the pull-up transistor and the second output node.

公开(公告)号：US11882742B2

公开(公告)日：2024-01-23

申请号：US17901516

申请日：2022-09-01

申请人： LG Display Co., Ltd.

发明人： Ki Min Son ,  Seok Noh ,  Ki Bok Park ,  Ye Won Hong

IPC分类号： G09G3/20 ,  H10K59/131 ,  G09G3/3266 ,  G11C19/28 ,  H10K59/124

CPC分类号： H10K59/1315 ,  G09G3/2096 ,  G09G3/3266 ,  G11C19/28 ,  G09G2300/0426 ,  G09G2310/0286 ,  G09G2310/0291 ,  G09G2330/021 ,  H10K59/124

摘要： A display panel and an electronic device including the same are disclosed. A circuit layer of the display panel includes at least a first transistor and a second transistor. The first transistor includes a first oxide semiconductor pattern, a gate electrode, a first electrode in contact with one side of the first oxide semiconductor pattern, a second electrode in contact with the other side of the first oxide semiconductor pattern, and a first-first metal pattern disposed on the substrate to overlap the first oxide semiconductor pattern. The second transistor includes a second oxide semiconductor pattern, a gate electrode, a first electrode in contact with one side of the second oxide semiconductor pattern, a second electrode in contact with the other side of the second oxide semiconductor pattern, a first-second metal pattern disposed on the substrate to overlap the second oxide semiconductor pattern, and a second metal pattern disposed between the second oxide semiconductor pattern and the first-second metal pattern.

公开(公告)号：US11830441B2

公开(公告)日：2023-11-28

申请号：US17861027

申请日：2022-07-08

申请人： LG Display Co., Ltd.

发明人： Ki Won Son ,  Ki Min Son ,  Seok Noh

IPC分类号： G09G3/3291 ,  G09G3/3266

CPC分类号： G09G3/3291 ,  G09G3/3266 ,  G09G2300/0842

摘要： The present disclosure is directed to a gate driver circuit configured to prevent a light-emitting element of a display device from emitting light in a sensing mode. The gate driver circuit allows a plurality of scan lines of the display device being concurrently sensed by pre-charging a node of the gate driver circuit prior starting a sensing mode. The present disclosure provides the benefit of sensing a greater number of pixels of a display in a shorter time while also ensuring that a sufficient charge is provided by the pre-charged node for a plurality of pixels of the plurality of scan lines to be sensed concurrently.

公开(公告)号：US10777143B2

公开(公告)日：2020-09-15

申请号：US16548761

申请日：2019-08-22

申请人： LG Display Co., Ltd.

发明人： Myungho Ban ,  Inhyo Han ,  Seok Noh ,  Kimin Son

IPC分类号： G09G3/3266 ,  G09G3/3233 ,  G09G3/3283 ,  G09G3/3291 ,  G09G3/3258

摘要： A gate driver includes a gate shift register in which an A block and a B block each having a plurality of stages, the A block and the B block being alternately arranged; scan clock lines inputting a first scan clock group and a second scan clock group each including both image data writing (IDW) scan clocks synchronized with an image write timing and black data insertion (BDI) scan clocks synchronized with a black write timing to the A block and the B block; and carry clock lines inputting carry clocks to the A block and the B block and sense clock lines inputting sense clocks to the A block and the B block, wherein each of the stages belonging to the A block and the B block includes a BDI memory storing a BDI carry signal for outputting the BDI scan clocks.

公开(公告)号：US11955085B2

公开(公告)日：2024-04-09

申请号：US17859947

申请日：2022-07-07

申请人： LG Display Co., Ltd.

发明人： Seok Noh ,  Ki Min Son

IPC分类号： G09G3/3266 ,  G09G3/3233

CPC分类号： G09G3/3266 ,  G09G3/3233 ,  G09G2300/0842 ,  G09G2310/0297 ,  G09G2310/08 ,  G09G2320/0247 ,  G09G2320/043 ,  G09G2320/0673 ,  G09G2330/021

摘要： An inverter circuit, a gate driver using the same, and a display device according to an embodiment are discussed. The inverter circuit can include a first transistor connected between a high potential voltage line and a first node; a second transistor having a gate connected to the first node and turned on according to a voltage of the first node to charge a second control node to a high potential voltage of the high potential voltage line; a third transistor having a gate connected to a first control node, a first electrode connected to the first node, and a second electrode connected to the second control node; and a fourth transistor having a gate connected to the first control node, a first electrode connected to the second control node, and a second electrode connected to a low potential voltage line.