公开(公告)号：US11031467B2

公开(公告)日：2021-06-08

申请号：US15930804

申请日：2020-05-13

Applicant: Korea Advanced Institute of Science and Technology

Inventor： Yang-Kyu Choi ,  Byung-Hyun Lee ,  Min-Ho Kang

IPC: H01L29/06 ,  H01L29/786 ,  H01L29/423 ,  H01L21/3065 ,  H01L21/265 ,  H01L21/324 ,  H01L21/027 ,  H01L21/311 ,  H01L21/3105 ,  H01L29/66 ,  H01L29/78 ,  H01L21/02 ,  H01L21/28 ,  H01L21/308 ,  H01L29/417

Abstract: Disclosed is a field effect transistor based on vertically integrated gate-all-around multiple nanowire channels including forming vertically integrated multiple nanowire channels in which a plurality of nanowires is vertically integrated, forming an interlayer dielectric layer (ILD) on the vertically integrated multiple nanowire channels, forming a hole in the interlayer dielectric layer such that at least some of the vertically integrated multiple nanowire channels are exposed, and forming a gate dielectric layer on the interlayer dielectric layer to fill the hole, wherein the forming of the gate dielectric layer on the interlayer dielectric layer to fill the hole includes depositing the gate dielectric layer on the interlayer dielectric layer to surround at least some of the vertically integrated multiple nanowire channels that are exposed though the hole. Nanowires may include various shapes of current channels that have efficient structures for current path. The cross section of the nanowire can be one of a circle shape, squared shape, rectangular shape, round shape, triangular shape, rhombus shape, eclipse shape, and others.

公开(公告)号：US20200303519A1

公开(公告)日：2020-09-24

申请号：US15930804

申请日：2020-05-13

Applicant: Korea Advanced Institute of Science and Technology

Inventor： Yang-Kyu CHOI ,  Byung-Hyun LEE ,  Min-Ho Kang

IPC: H01L29/66 ,  H01L29/06 ,  H01L29/423 ,  H01L29/417 ,  H01L29/786 ,  H01L21/02 ,  H01L21/265 ,  H01L21/3065 ,  H01L21/308 ,  H01L21/324 ,  H01L21/3105 ,  H01L21/311 ,  H01L21/28

Abstract: Disclosed is a field effect transistor based on vertically integrated gate-all-around multiple nanowire channels including forming vertically integrated multiple nanowire channels in which a plurality of nanowires is vertically integrated, forming an interlayer dielectric layer (ILD) on the vertically integrated multiple nanowire channels, forming a hole in the interlayer dielectric layer such that at least some of the vertically integrated multiple nanowire channels are exposed, and forming a gate dielectric layer on the interlayer dielectric layer to fill the hole, wherein the forming of the gate dielectric layer on the interlayer dielectric layer to fill the hole includes depositing the gate dielectric layer on the interlayer dielectric layer to surround at least some of the vertically integrated multiple nanowire channels that are exposed though the hole. Nanowires may include various shapes of current channels that have efficient structures for current path. The cross section of the nanowire can be one of a circle shape, squared shape, rectangular shape, round shape, triangular shape, rhombus shape, eclipse shape, and others.

公开(公告)号：US10665671B2

公开(公告)日：2020-05-26

申请号：US15428727

申请日：2017-02-09

Applicant: Korea Advanced Institute of Science and Technology

Inventor： Yang-Kyu Choi ,  Byung-Hyun Lee ,  Min-Ho Kang

IPC: H01L21/00 ,  H01L29/06 ,  H01L29/423 ,  H01L21/3065 ,  H01L21/265 ,  H01L21/324 ,  H01L21/027 ,  H01L21/311 ,  H01L21/3105 ,  H01L29/66 ,  H01L29/786 ,  H01L29/78

Abstract: Disclosed is a method of manufacturing a junctionless transistor based on vertically integrated gate-all-around multiple nanowire channels including forming vertically integrated multiple nanowire channels in which a plurality of nanowires is vertically integrated, forming an interlayer dielectric layer (ILD) on the vertically integrated multiple nanowire channels, forming a hole in the interlayer dielectric layer such that at least some of the vertically integrated multiple nanowire channels is exposed, and forming a gate dielectric layer on the interlayer dielectric layer to fill the hole, wherein the forming of the gate dielectric layer on the interlayer dielectric layer to fill the hole includes depositing the gate dielectric layer on the interlayer dielectric layer to surround at least some of the vertically integrated multiple nanowire channels which is exposed though the hole.

公开(公告)号：US20170236901A1

公开(公告)日：2017-08-17

申请号：US15428727

申请日：2017-02-09

Applicant: Korea Advanced Institute of Science and Technology

Inventor： Yang-Kyu Choi ,  Byung-Hyun Lee ,  Min-Ho Kang

IPC: H01L29/06 ,  H01L21/3065 ,  H01L21/265 ,  H01L21/324 ,  H01L29/78 ,  H01L21/311 ,  H01L21/3105 ,  H01L29/66 ,  H01L29/786 ,  H01L29/423 ,  H01L21/027

CPC classification number: H01L29/0673 ,  H01L21/0274 ,  H01L21/26513 ,  H01L21/3065 ,  H01L21/31055 ,  H01L21/31111 ,  H01L21/31116 ,  H01L21/324 ,  H01L29/42392 ,  H01L29/66439 ,  H01L29/78696

Abstract: Disclosed is a method of manufacturing a junctionless transistor based on vertically integrated gate-all-around multiple nanowire channels including forming vertically integrated multiple nanowire channels in which a plurality of nanowires is vertically integrated, forming an interlayer dielectric layer (ILD) on the vertically integrated multiple nanowire channels, forming a hole in the interlayer dielectric layer such that at least some of the vertically integrated multiple nanowire channels is exposed, and forming a gate dielectric layer on the interlayer dielectric layer to fill the hole, wherein the forming of the gate dielectric layer on the interlayer dielectric layer to fill the hole includes depositing the gate dielectric layer on the interlayer dielectric layer to surround at least some of the vertically integrated multiple nanowire channels which is exposed though the hole.