公开(公告)号：US20110220978A1

公开(公告)日：2011-09-15

申请号：US12876598

申请日：2010-09-07

Applicant: Kentaro IKEDA ,  Masahiko Kuraguchi

Inventor： Kentaro IKEDA ,  Masahiko Kuraguchi

IPC: H01L27/06 ,  H01L29/24 ,  H01L29/20

CPC classification number: H01L27/0605 ,  H01L27/0629 ,  H01L29/1608 ,  H01L29/2003 ,  H01L29/7786

Abstract: In an embodiment, provided is a semiconductor device in which a normally-on type FET; a capacitor having one electrode electrically connected to a gate of the FET and the other electrode electrically connected to an input terminal; and a diode having an anode electrode electrically connected to the gate of the FET and a cathode electrode electrically connected to a source of the FET are formed on the same chip on which the FET is formed. Also, the capacitor may have a structure in which an insulation film such as a dielectric substance is formed on a gate drawn electrode of the FET, and a metallic layer is formed on the insulation layer.

Abstract translation: 在一个实施例中，提供了一种半导体器件，其中常导型FET; 电容器，其一个电极与FET的栅极电连接，另一个电极与输入端电连接; 并且在与FET的栅极电连接的阳极电极和与FET的源极电连接的阴极电极的二极管形成在形成有FET的同一芯片上。 此外，电容器可以具有其中在FET的栅极拉制电极上形成诸如电介质的绝缘膜的结构，并且在绝缘层上形成金属层。

公开(公告)号：US20130062611A1

公开(公告)日：2013-03-14

申请号：US13397887

申请日：2012-02-16

Applicant: Kentaro IKEDA ,  Mayumi Morizuka

Inventor： Kentaro IKEDA ,  Mayumi Morizuka

IPC: H01L29/20

CPC classification number: H01L29/2003 ,  H01L29/205 ,  H01L29/861

Abstract: A semiconductor device of an embodiment includes: a first semiconductor layer made of AlXGa1-XN (0

Abstract translation: 实施例的半导体器件包括：由Al x Ga 1-x N（0

公开(公告)号：US20120228625A1

公开(公告)日：2012-09-13

申请号：US13220005

申请日：2011-08-29

Applicant: Kentaro IKEDA

Inventor： Kentaro IKEDA

IPC: H01L29/20

CPC classification number: H01L29/7786 ,  H01L27/0605 ,  H01L27/0629 ,  H01L27/088 ,  H01L28/20 ,  H01L29/2003 ,  H01L29/205 ,  H01L29/41758 ,  H01L29/861 ,  H01L29/94 ,  H03K17/0406 ,  H03K17/0412 ,  H03K17/567

Abstract: According to one embodiment, a nitride semiconductor device includes a first, a second, a third and a fourth transistor of n-type channel and a resistor. The first transistor has a first gate, a first source, and a first drain. The second transistor has a second gate, a second source electrically connected to the first gate, and a second drain. The third transistor has a third gate, a third source electrically connected to the first source, and a third drain electrically connected to the first gate and the second source. The fourth transistor has a fourth gate electrically connected to the third gate, a fourth source electrically connected to the first source and the third source, and a fourth drain electrically connected to the second gate. The resistor has one end electrically connected to the second drain and one other end electrically connected to the second gate and the fourth drain.

Abstract translation: 根据一个实施例，氮化物半导体器件包括n型沟道的第一，第二，第三和第四晶体管和电阻器。 第一晶体管具有第一栅极，第一源极和第一漏极。 第二晶体管具有第二栅极，电连接到第一栅极的第二源极和第二漏极。 第三晶体管具有第三栅极，电连接到第一源极的第三源极和与第一栅极和第二源极电连接的第三漏极。 第四晶体管具有电连接到第三栅极的第四栅极，与第一源极和第三源极电连接的第四源极和与第二栅极电连接的第四漏极。 电阻器的一端电连接到第二漏极，另一端电连接到第二栅极和第四漏极。

公开(公告)号：US20110221480A1

公开(公告)日：2011-09-15

申请号：US12881842

申请日：2010-09-14

Applicant: Kentaro IKEDA

Inventor： Kentaro IKEDA

IPC: H03K3/02

CPC classification number: H03K17/04123 ,  H03K2217/009

Abstract: A resonant gate drive circuits for a voltage controlled transistor according to the embodiments are characterized by connecting a resonant inductor and a resistor to a gate of the voltage controlled transistor or a gate of the normally-on voltage controlled transistor or a voltage control terminal of a pseudo normally-off element, in series, and providing the drive circuit with two complementary switching elements connected in series.

Abstract translation: 根据实施例的用于电压控制晶体管的谐振栅极驱动电路的特征在于将谐振电感器和电阻器连接到电压控制晶体管的栅极或常导通电压控制晶体管的栅极或者电压控制晶体管的电压控制端子 伪常关断元件，并且为驱动电路提供串联连接的两个互补开关元件。

公开(公告)号：US20120200339A1

公开(公告)日：2012-08-09

申请号：US13215608

申请日：2011-08-23

Applicant: Kentaro IKEDA

Inventor： Kentaro IKEDA

IPC: H03K17/06

CPC classification number: G05F3/242

Abstract: A reference-voltage generating circuit of an embodiment includes a first FET; a second FET; a first resistor in which one end is connected to a power supply while the other end is connected to a drain of the first FET; and a second resistor that is connected between the drain and a gate of the first FET, wherein a gate and a source of the second FET are connected, a drain of the second FET is connected to the gate of the first FET, the drain of the first FET outputs a reference voltage, and the source of the first FET and the source of the second FET are connected to a ground or another circuit.

Abstract translation: 实施例的参考电压产生电路包括第一FET; 第二FET; 第一电阻器，其一端连接到电源，而另一端连接到第一FET的漏极; 以及连接在第一FET的漏极和栅极之间的第二电阻器，其中连接第二FET的栅极和源极，第二FET的漏极连接到第一FET的栅极，漏极 第一FET输出参考电压，第一FET的源极和第二FET的源极连接到地或另一个电路。

公开(公告)号：US20110216352A1

公开(公告)日：2011-09-08

申请号：US12878294

申请日：2010-09-09

Applicant: Kentaro IKEDA

Inventor： Kentaro IKEDA

IPC: G06F3/12

CPC classification number: G03G15/238 ,  G03G15/0178 ,  G03G15/0194 ,  G03G2215/00021

Abstract: An image formation control apparatus includes a management unit, a communication unit, and a control unit. The management unit manages first image formation processing on a first face of a planar recording medium. The first image formation processing is performed by a first image formation apparatus. The communication unit communicates with a second image forming apparatus configured to perform image formation on a second face of the planar recording medium. The control unit performs control of transportation of the planar recording medium from the first image formation apparatus to the second image formation apparatus or from the second image formation apparatus. A first amount of time to start image formation from receiving an image formation instruction in the first image formation apparatus is smaller that a second amount of time to start image formation from receiving an image formation instruction in the second image formation apparatus.

Abstract translation: 图像形成控制装置包括管理单元，通信单元和控制单元。 管理单元在平面记录介质的第一面上管理第一图像形成处理。 第一图像形成处理由第一图像形成装置执行。 通信单元与被配置为在平面记录介质的第二面上进行图像形成的第二图像形成装置进行通信。 控制单元执行平面记录介质从第一图像形成装置到第二图像形成装置或第二图像形成装置的传送的控制。 在第一图像形成装置中从接收图像形成指令开始图像形成的第一时间量小于在第二图像形成装置中从接收图像形成指令开始图像形成的第二时间量。