公开(公告)号：US20180006920A1

公开(公告)日：2018-01-04

申请号：US15693045

申请日：2017-08-31

Applicant: Juniper Networks, Inc.

Inventor： Avanindra GODBOLE ,  Jainendra Kumar ,  Gregory M. Waters

IPC: H04L12/26 ,  H04L12/801 ,  H04L12/875

CPC classification number: H04L43/0858 ,  H04L43/0876 ,  H04L43/106 ,  H04L47/11 ,  H04L47/283 ,  H04L47/562

Abstract: An output circuit, included in a device, may determine counter information associated with a packet provided via an output queue managed by the output circuit. The output circuit may determine that a latency event, associated with the output queue, has occurred. The output circuit may provide the counter information and time of day information associated with the counter information. The output circuit may provide a latency event notification associated with the output queue. An input circuit, included in the device, may receive the latency event notification associated with the output queue. The input circuit may determine performance information associated with an input queue. The input queue may correspond to the output queue and may be managed by the input circuit. The input circuit may provide the performance information associated with the input queue and time of day information associated with the performance information.

公开(公告)号：US09755932B1

公开(公告)日：2017-09-05

申请号：US14498440

申请日：2014-09-26

Applicant: Juniper Networks, Inc.

Inventor： Avanindra Godbole ,  Jainendra Kumar ,  Gregory M. Waters

IPC: H04L12/26 ,  H04L12/875 ,  H04L12/801

CPC classification number: H04L43/0858 ,  H04L43/0876 ,  H04L43/106 ,  H04L47/11 ,  H04L47/283 ,  H04L47/562

Abstract: An output circuit, included in a device, may determine counter information associated with a packet provided via an output queue managed by the output circuit. The output circuit may determine that a latency event, associated with the output queue, has occurred. The output circuit may provide the counter information and time of day information associated with the counter information. The output circuit may provide a latency event notification associated with the output queue. An input circuit, included in the device, may receive the latency event notification associated with the output queue. The input circuit may determine performance information associated with an input queue. The input queue may correspond to the output queue and may be managed by the input circuit. The input circuit may provide the performance information associated with the input queue and time of day information associated with the performance information.