公开(公告)号：US20160211937A1

公开(公告)日：2016-07-21

申请号：US15084146

申请日：2016-03-29

Applicant: Juniper Networks, Inc.

Inventor： Charles F. Barry ,  Meenakshi S. Subramanian ,  Feng Frank Pan ,  Tian (Alan) Shen ,  Philip Kruzinski ,  Guochun (George) Zhao ,  DeviPrasad Natesan ,  David R. Jorgensen

IPC: H04J3/06

CPC classification number: H04J3/0682 ,  H04J3/0667

Abstract: An apparatus and method are described for compensating for frequency and phase variations of electronic components by processing packet delay values. In one embodiment, a packet delay determination module determines packet delay values based on time values associated with a first and a second electronic component. A packet delay selection module selects a subset of the packet delay values based on the maximum frequency drift of the first electronic component. A statistical parameter determination module evaluates a first and a second parameter based on portions of the subset of packet delay values. A validation module validates the parameters when each portion the subset of packet delay values includes a minimum of at least two packet delay values. An adjustment module compensates for at least one of a frequency variation and a phase variation of the first electronic component based on the parameters if the parameters are both validated.

公开(公告)号：US20130301660A1

公开(公告)日：2013-11-14

申请号：US13944788

申请日：2013-07-17

Applicant: Juniper Networks, Inc.

Inventor： Charles F. Barry ,  Meenakshi S. Subramanian ,  Feng Frank Pan ,  Tian (Alan) Shen ,  Philip Kruzinski ,  Guochun (George) Zhao ,  DeviPrasad Natesan ,  David R. Jorgensen

IPC: H04J3/06

CPC classification number: H04J3/0682 ,  H04J3/0667

Abstract: An apparatus and method are described for compensating for frequency and phase variations of electronic components by processing packet delay values. In one embodiment, a packet delay determination module determines packet delay values based on time values associated with a first and a second electronic component. A packet delay selection module selects a subset of the packet delay values based on the maximum frequency drift of the first electronic component. A statistical parameter determination module evaluates a first and a second parameter based on portions of the subset of packet delay values. A validation module validates the parameters when each portion the subset of packet delay values includes a minimum of at least two packet delay values. An adjustment module compensates for at least one of a frequency variation and a phase variation of the first electronic component based on the parameters if the parameters are both validated.

Abstract translation: 描述了通过处理分组延迟值来补偿电子部件的频率和相位变化的装置和方法。 在一个实施例中，分组延迟确定模块基于与第一和第二电子组件相关联的时间值来确定分组延迟值。 分组延迟选择模块基于第一电子部件的最大频率漂移来选择分组延迟值的子集。 统计参数确定模块基于分组延迟值的子集的部分来评估第一和第二参数。 验证模块在分组延迟值的子集包括至少两个分组延迟值的最小值的每个部分时验证参数。 如果参数都被验证，则调整模块基于参数补偿第一电子部件的频率变化和相位变化中的至少一个。

公开(公告)号：US10284318B1

公开(公告)日：2019-05-07

申请号：US16002607

申请日：2018-06-07

Applicant: Juniper Networks, Inc.

Inventor： Abhijit Kumar Choudhury ,  Murthy Garikiparthi ,  DeviPrasad Natesan ,  James Michael Murphy ,  Meenakshi Sundaram Subramanian

IPC: H04J3/06 ,  H04L12/751 ,  H04L12/24 ,  H04L12/911

Abstract: In one example, a network controller manages a network having many network devices. Network devices can receive the timing flow port role assignments from the network controller based on the controller's global view of the network topology. The controller can also calculate timing offsets to be applied to the network devices, based on timestamp information obtained by the network devices via exchanging time synchronization protocol messages, and the controller can update time clocks on all of the network devices within a single window of time, based on a timing offsets calculated in single iteration of calculations.

公开(公告)号：US09998247B1

公开(公告)日：2018-06-12

申请号：US14586507

申请日：2014-12-30

Applicant: Juniper Networks, Inc.

Inventor： Abhijit Kumar Choudhury ,  Murthy Garikiparthi ,  DeviPrasad Natesan ,  James Michael Murphy ,  Meenakshi Sundaram Subramanian

IPC: H04J3/06 ,  H04L12/911 ,  H04L12/24 ,  H04L12/751

CPC classification number: H04J3/0685 ,  H04J3/0602 ,  H04L41/085 ,  H04L45/02 ,  H04L47/828

Abstract: In one example, a network controller manages a network having many network devices. Network devices can receive the timing flow port role assignments from the network controller based on the controller's global view of the network topology. The controller can also calculate timing offsets to be applied to the network devices, based on timestamp information obtained by the network devices via exchanging time synchronization protocol messages, and the controller can update time clocks on all of the network devices within a single window of time, based on a timing offsets calculated in single iteration of calculations.

公开(公告)号：US09621290B2

公开(公告)日：2017-04-11

申请号：US15084146

申请日：2016-03-29

Applicant: Juniper Networks, Inc.

Inventor： Charles F. Barry ,  Meenakshi S. Subramanian ,  Feng Frank Pan ,  Tian (Alan) Shen ,  Philip Kruzinski ,  Guochun (George) Zhao ,  DeviPrasad Natesan ,  David R. Jorgensen

IPC: H04J3/06

CPC classification number: H04J3/0682 ,  H04J3/0667

Abstract: An apparatus and method are described for compensating for frequency and phase variations of electronic components by processing packet delay values. In one embodiment, a packet delay determination module determines packet delay values based on time values associated with a first and a second electronic component. A packet delay selection module selects a subset of the packet delay values based on the maximum frequency drift of the first electronic component. A statistical parameter determination module evaluates a first and a second parameter based on portions of the subset of packet delay values. A validation module validates the parameters when each portion the subset of packet delay values includes a minimum of at least two packet delay values. An adjustment module compensates for at least one of a frequency variation and a phase variation of the first electronic component based on the parameters if the parameters are both validated.

公开(公告)号：US09319164B2

公开(公告)日：2016-04-19

申请号：US13944788

申请日：2013-07-17

Applicant: Juniper Networks, Inc.

Inventor： Charles F. Barry ,  Meenakshi S. Subramanian ,  Feng Frank Pan ,  Tian (Alan) Shen ,  Philip Kruzinski ,  Guochun (George) Zhao ,  DeviPrasad Natesan ,  David R. Jorgensen

IPC: H04J3/06

CPC classification number: H04J3/0682 ,  H04J3/0667

Abstract: An apparatus and method are described for compensating for frequency and phase variations of electronic components by processing packet delay values. In one embodiment, a packet delay determination module determines packet delay values based on time values associated with a first and a second electronic component. A packet delay selection module selects a subset of the packet delay values based on the maximum frequency drift of the first electronic component. A statistical parameter determination module evaluates a first and a second parameter based on portions of the subset of packet delay values. A validation module validates the parameters when each portion the subset of packet delay values includes a minimum of at least two packet delay values. An adjustment module compensates for at least one of a frequency variation and a phase variation of the first electronic component based on the parameters if the parameters are both validated.