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1.发明授权DC-DC converter efficiency improvement and area reduction using a novel switching technique 有权DC-DC转换器的效率提高和使用新颖的切换技术的面积减少公开(公告)号：US09312758B2
公开(公告)日：2016-04-12
申请号：US12661515
申请日：2010-03-18
Applicant: Julian Tyrrell , Biren Minhas , Anna Hedley , Stuart Levine
Inventor： Julian Tyrrell , Biren Minhas , Anna Hedley , Stuart Levine
Abstract: A control logic of a switched DC-to-DC converter allows continuous switching to bring the DC-to-DC converter to a final output value during a startup phase, it allows skipping of clock switching pulses if they are not needed and allows burst mode of switching pulses dependent on a load applied to the output voltage of the DC-to-DC converter. No digital or analog regulator is required for the control logic.
Abstract translation: 开关DC-DC转换器的控制逻辑允许连续切换，使DC-DC转换器在启动阶段达到最终的输出值，如果不需要时可以跳过时钟切换脉冲，并允许突发模式 取决于施加到DC-DC转换器的输出电压的负载的开关脉冲。 控制逻辑不需要数字或模拟调节器。
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2.发明申请DC-DC converter efficiency improvement and area reduction using a novel switching technique 有权DC-DC转换器的效率提高和使用新颖的切换技术的面积减少公开(公告)号：US20110204861A1
公开(公告)日：2011-08-25
申请号：US12661515
申请日：2010-03-18
Applicant: Julian Tyrrell , Biren Minhas , Anna Hedley , Stuart Levine
Inventor： Julian Tyrrell , Biren Minhas , Anna Hedley , Stuart Levine
IPC: G05F1/10
Abstract: Systems and methods to achieve a switched DC-to-DC converter having an improved efficiency have been disclosed. A control logic allows continuous switching to bring the DC-to-DC converter to a final output value during a startup phase, it allows skipping of clock switching pulses if they are not needed and allows burst mode of switching pulses dependent on a load applied to the output voltage of the DC-to-DC converter. No digital or analog regulator is required for the control logic.
Abstract translation: 已经公开了实现具有改进的效率的开关式DC-DC转换器的系统和方法。 控制逻辑允许连续切换在启动阶段使DC-DC转换器达到最终的输出值，如果不需要时可以跳过时钟切换脉冲，并允许脉冲串模式的开关脉冲取决于施加到 DC-DC转换器的输出电压。 控制逻辑不需要数字或模拟调节器。
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公开(公告)号：US09151804B2
公开(公告)日：2015-10-06
申请号：US13443919
申请日：2012-04-11
Applicant: Dietmar Orendi , Biren Minhas , Robert Baraniecki
Inventor： Dietmar Orendi , Biren Minhas , Robert Baraniecki
IPC: G01R19/00 , G01R31/40 , G01R31/317
CPC classification number: G01R31/40 , G01R31/2834 , G01R31/31721 , G05F1/56
Abstract: A circuit and method is described for automatically testing multiple LDO regulator circuits on an integrated circuit chip independent of an ATE. Each LDO regulator is tested for voltage at a specified current output capability, wherein the output driver transistor is formed by at least two pass transistors, which are each tested for voltage output at a particular current capability. The test results are delivered back to the ATE and for a failed test, the gate voltage of the pass device can be observed through an analog multiplexer to enable debug.
Abstract translation: 描述了一种用于在独立于ATE的集成电路芯片上自动测试多个LDO稳压器电路的电路和方法。 每个LDO调节器以指定的电流输出能力测试电压，其中输出驱动器晶体管由至少两个传输晶体管形成，每个晶体管都以特定电流能力测试电压输出。 测试结果被传送回ATE，对于失败的测试，可以通过模拟多路复用器观察通过器件的栅极电压，以启用调试。
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公开(公告)号：US20130265060A1
公开(公告)日：2013-10-10
申请号：US13443919
申请日：2012-04-11
Applicant: Dietmar Orendi , Biren Minhas , Robert Baraniecki
Inventor： Dietmar Orendi , Biren Minhas , Robert Baraniecki
IPC: G01R31/02
CPC classification number: G01R31/40 , G01R31/2834 , G01R31/31721 , G05F1/56
Abstract: A circuit and method is described for automatically testing multiple LDO regulator circuits on an integrated circuit chip independent of an ATE. Each LDO regulator is tested for voltage at a specified current output capability, wherein the output driver transistor is formed by at least two pass transistors, which are each tested for voltage output at a particular current capability. The test results are delivered back to the ATE and for a failed test, the gate voltage of the pass device can be observed through an analog multiplexer to enable debug.
Abstract translation: 描述了一种用于在独立于ATE的集成电路芯片上自动测试多个LDO稳压器电路的电路和方法。 每个LDO调节器以指定的电流输出能力测试电压，其中输出驱动器晶体管由至少两个传输晶体管形成，每个晶体管都以特定电流能力测试电压输出。 测试结果被传送回ATE，对于失败的测试，可以通过模拟多路复用器观察通过器件的栅极电压，以启用调试。
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