PASSIVATION LAYER FOR SEMICONDUCTOR DEVICES
    1.
    发明申请
    PASSIVATION LAYER FOR SEMICONDUCTOR DEVICES 有权
    半导体器件的钝化层

    公开(公告)号:US20120217633A1

    公开(公告)日:2012-08-30

    申请号:US13036897

    申请日:2011-02-28

    IPC分类号: H01L23/485 H01L21/768

    摘要: An embodiment of the disclosure provides a semiconductor device. The semiconductor device includes a plurality of metallization layers comprising a topmost metallization layer. The topmost metallization layer has two metal features having a thickness T1 and being separated by a gap. A composite passivation layer comprises a HDP CVD oxide layer under a nitride layer. The composite passivation layer is disposed over the metal features and partially fills the gap. The composite passivation layer has a thickness T2 about 20% to 50% of the thickness T1.

    摘要翻译: 本公开的实施例提供一种半导体器件。 半导体器件包括多个金属化层,其包括最上面的金属化层。 最上面的金属化层具有两个具有厚度T1并被间隙隔开的金属特征。 复合钝化层包括氮化物层下的HDP CVD氧化物层。 复合钝化层设置在金属特征上并部分填充间隙。 复合钝化层的厚度T2约为厚度T1的20%至50%。