公开(公告)号：US20080012044A1

公开(公告)日：2008-01-17

申请号：US11691018

申请日：2007-03-26

申请人： Javier SALCEDO ,  Juin Liou ,  Joseph Bernier ,  Donald Whitney

发明人： Javier SALCEDO ,  Juin Liou ,  Joseph Bernier ,  Donald Whitney

IPC分类号： H01L29/72 ,  H01L29/74

CPC分类号： H01L27/0262 ,  H01L29/7436

摘要： A complementary SCR-based structure enables a tunable holding voltage for robust and versatile ESD protection. The structureare n-channel high-holding-voltage low-voltage -trigger silicon controller rectifier (N-HHLVTSCR) device and p-channel high-holding-voltage low-voltage -trigger silicon controller rectifier (P-HHLVTSCR) device. The regions of the N-HHLVTSCR and P-HHLVTSCR devices are formed during normal processing steps in a CMOS or BICMOS process. The spacing and dimensions of the doped regions of N-HHLVTSCR and P-HHLVTSCR devices are used to produce the desired characteristics. The tunable HHLVTSCRs makes possible the use of this protection circuit in a broad range of ESD applications including protecting integrated circuits where the I/O signal swing can be either within the range of the bias of the internal circuit or below/above the range of the bias of the internal circuit.

摘要翻译： 互补的基于SCR的结构使得可调谐的保持电压具有稳健和通用的ESD保护。 结构为n沟道高压保护电压低电压触发器硅控整流器（N-HHLVTSCR）器件和p沟道高保持电压低电压触发器硅控整流器（P-HHLVTSCR）器件。 N-HHLVTSCR和P-HHLVTSCR器件的区域在CMOS或BICMOS工艺的正常处理步骤期间形成。 使用N-HHLVTSCR和P-HHLVTSCR器件的掺杂区域的间距和尺寸来产生所需的特性。 可调谐的HHLVTSCR可以在广泛的ESD应用中使用该保护电路，包括保护集成电路，其中I / O信号摆幅可以在内部电路的偏置范围内或低于/高于 内部电路的偏置。

公开(公告)号：US20050151160A1

公开(公告)日：2005-07-14

申请号：US11032154

申请日：2005-01-11

申请人： Javier Salcedo ,  Juin Liou ,  Joseph Bernier ,  Donald Whitney

发明人： Javier Salcedo ,  Juin Liou ,  Joseph Bernier ,  Donald Whitney

IPC分类号： H01L27/02 ,  H01L29/72

CPC分类号： H01L27/0262 ,  H01L29/7436

摘要： A complementary SCR-based structure enables a tunable holding voltage for robust and versatile ESD protection. The structure are n-channel high-holding-voltage low-voltage-trigger silicon controller rectifier (N-HHLVTSCR) device and p-channel high-holding-voltage low-voltage-trigger silicon controller rectifier (P-HHLVTSCR) device. The regions of the N-HHLVTSCR and P-HHLVTSCR devices are formed during normal processing steps in a CMOS or BICMOS process. The spacing and dimensions of the doped regions of N-HHLVTSCR and P-HHLVTSCR devices are used to produce the desired characteristics. The tunable HHLVTSCRs makes possible the use of this protection circuit in a broad range of ESD applications including protecting integrated circuits where the I/O signal swing can be either within the range of the bias of the internal circuit or below/above the range of the bias of the internal circuit.

摘要翻译： 互补的基于SCR的结构使得可调谐的保持电压具有稳健和通用的ESD保护。 结构是n沟道高保持电压低压触发硅控整流器（N-HHLVTSCR）器件和p沟道高保持电压低压触发硅控整流器（P-HHLVTSCR）器件。 N-HHLVTSCR和P-HHLVTSCR器件的区域在CMOS或BICMOS工艺的正常处理步骤期间形成。 使用N-HHLVTSCR和P-HHLVTSCR器件的掺杂区域的间距和尺寸来产生所需的特性。 可调谐的HHLVTSCR可以在广泛的ESD应用中使用该保护电路，包括保护集成电路，其中I / O信号摆幅可以在内部电路的偏置范围内或低于/高于 内部电路的偏置。

公开(公告)号：US20060151836A1

公开(公告)日：2006-07-13

申请号：US11330139

申请日：2006-01-12

申请人： Javier Salcedo ,  Juin Liou ,  Joseph Bernier ,  Donald Whitney

发明人： Javier Salcedo ,  Juin Liou ,  Joseph Bernier ,  Donald Whitney

IPC分类号： H01L23/62

CPC分类号： H01L29/7436 ,  H01L27/0262 ,  H01L2924/0002 ,  H01L2924/00

摘要： An electrostatic discharge (ESD) device and method is provided. The ESD device can comprise a substrate doped to a first conductivity type, an epitaxial region doped to the second conductivity type, and a first well doped to the first conductivity type disposed in the substrate. The first well can comprise a first region doped to the first conductivity type, a second region doped to a second conductivity type, and a first isolation region disposed between the first region and the second region. The ESD device can also comprise a second well doped to a second conductivity type disposed in the substrate adjacent to the first well, where the second well can comprise a third region doped to the first conductivity type, a fourth region doped to the second conductivity type, and a second isolation region disposed between the third region and the fourth region. Still further, the ESD device can include a first trigger contact and second trigger contact comprising highly doped regions of either conductivity type, the first trigger contact disposed at a junction between the first well and the second well, and the second trigger contact disposed at either well.

公开(公告)号：US20080044955A1

公开(公告)日：2008-02-21

申请号：US11871269

申请日：2007-10-12

申请人： Javier Salcedo ,  Juin Liou ,  Joseph Bernier ,  Donald Whitney

发明人： Javier Salcedo ,  Juin Liou ,  Joseph Bernier ,  Donald Whitney

IPC分类号： H01L21/332

CPC分类号： H01L29/7436 ,  H01L27/0262 ,  H01L2924/0002 ,  H01L2924/00

摘要： An electrostatic discharge (ESD) device and method is provided. The ESD device can comprise a substrate doped to a first conductivity type, an epitaxial region doped to the second conductivity type, and a first well doped to the first conductivity type disposed in the substrate. The first well can comprise a first region doped to the first conductivity type, a second region doped to a second conductivity type, and a first isolation region disposed between the first region and the second region. The ESD device can also comprise a second well doped to a second conductivity type disposed in the substrate adjacent to the first well, where the second well can comprise a third region doped to the first conductivity type, a fourth region doped to the second conductivity type, and a second isolation region disposed between the third region and the fourth region. Still further, the ESD device can include a first trigger contact and second trigger contact comprising highly doped regions of either conductivity type, the first trigger contact disposed at a junction between the first well and the second well, and the second trigger contact disposed at either well.

摘要翻译： 提供了静电放电（ESD）装置和方法。 ESD器件可以包括掺杂到第一导电类型的衬底，掺杂到第二导电类型的外延区域，以及掺杂到设置在衬底中的第一导电类型的第一阱。 第一阱可以包括掺杂到第一导电类型的第一区域，掺杂到第二导电类型的第二区域和设置在第一区域和第二区域之间的第一隔离区域。 ESD器件还可以包括掺杂到与第一阱相邻的衬底中的第二导电类型的第二阱，其中第二阱可以包括掺杂到第一导电类型的第三区域，掺杂到第二导电类型的第四区域 以及设置在第三区域和第四区域之间的第二隔离区域。 此外，ESD装置可以包括第一触发触点和第二触发触点，其包括导电类型的高掺杂区域，第一触发触点设置在第一阱和第二阱之间的接合处，第二触发触点设置在第二触发触点 好。

公开(公告)号：US20070007545A1

公开(公告)日：2007-01-11

申请号：US11289390

申请日：2005-11-30

申请人： Javier Salcedo ,  Juin Liou ,  Joseph Bernier ,  Donald Whitney

发明人： Javier Salcedo ,  Juin Liou ,  Joseph Bernier ,  Donald Whitney

IPC分类号： H01L29/74

CPC分类号： H01L27/0262 ,  H01L29/87

摘要： Symmetrical/asymmetrical bidirectional S-shaped I-V characteristics with trigger voltages ranging from 10 V to over 40 V and relatively high holding current are obtained for advanced sub-micron silicided CMOS (Complementary Metal Oxide Semiconductor)/BiCMOS (Bipolar CMOS) technologies by custom implementation of P1-N2-P2-N1//N1-P3-N3-P1 lateral structures with embedded ballast resistance 58, 58A, 56, 56A and periphery guard-ring isolation 88-86. The bidirectional protection devices render a high level of electrostatic discharge (ESD) immunity for advanced CMOS/BiCMOS processes with no latchup problems. Novel design-adapted multifinger 354/interdigitated 336 layout schemes of the ESD protection cells allow for scaling-up the ESD performance of the protection structure and custom integration, while the I-V characteristics 480 are adjustable to the operating conditions of the integrated circuit (IC). The ESD protection cells are tested using the TLP (Transmission Line Pulse) technique, and ESD standards including HBM (Human Body Model), MM (Machine Model), and IEC (International Electrotechnical Commission) IEC 1000-4-2 standard for ESD immunity. ESD protection performance is demonstrated also at high temperature (140° C.). The unique high ratio of dual-polarity ESD protection level per unit area, allows for integration of fast-response and compact protection cells optimized for the current tendency of the semiconductor industry toward low cost and high density-oriented IC design. Symmetric/asymmetric dual polarity ESD protection performance is demonstrated for over 15 kV HBM, 2 kV MM, and 16.5 kV IEC for sub-micron technology.