公开(公告)号：US20250006685A1

公开(公告)日：2025-01-02

申请号：US18740620

申请日：2024-06-12

Applicant: JCET Management Co., Ltd. ,  STATS ChipPAC Pte. Ltd.

Inventor： Zhan YING ,  Kai LIU ,  Yaqin WANG

IPC: H01L23/00 ,  H01L25/18 ,  H10B80/00

Abstract: A semiconductor package comprises: a package substrate having a front surface and a rear surface, wherein the package substrate comprises: a plurality sets of front conductive patterns formed on the front surface; and a plurality sets of interconnects electrically coupled to the plurality sets of front conductive patterns, respectively; a plurality of electronic components mounted to the front surface of the package substrate and electrically coupled to the plurality sets of front conductive patterns via a plurality sets of front conductive components, respectively; wherein the plurality sets of conductive components at least comprise a set of first-type conductive components and a set of second-type conductive components, wherein the set of first-type conductive components are connected to a first electronic component of the plurality of electronic components, and the set of second-type conductive components are connected to a second electronic component of the plurality of electronic components; and wherein a thermal conductivity of the first-type conductive components is higher than the second-type conductive components, and a power consumption of the first electronic component is higher than the second electronic component.

公开(公告)号：US20250006682A1

公开(公告)日：2025-01-02

申请号：US18740608

申请日：2024-06-12

Applicant: JCET Management Co., Ltd. ,  STATS ChipPAC Pte. Ltd.

Inventor： Zhan YING ,  Kai LIU ,  Yaqin WANG

IPC: H01L23/00 ,  H01L23/31 ,  H01L23/373 ,  H01L23/498 ,  H01L25/065

Abstract: A semiconductor package comprise: a package substrate having a front surface and a rear surface, wherein the package substrate comprises: a set of front conductive patterns formed on the front surface; a set of rear conductive patterns formed on the rear surface; and a set of interconnects electrically coupling the set of front conductive patterns with the set of rear conductive patterns, respectively; at least one electronic component mounted on the front surface of the package substrate and electrically coupled to the set of front conductive patterns via a set of front solder balls; a set of rear solder balls electrically connected to the set of rear conductive patterns, respectively; wherein the set of front solder balls comprises one or more first-type solder balls and one or more second-type solder balls, and the set of rear solder balls comprises one or more first-type solder balls and one or more second-type solder balls; and wherein the first-type solder balls of the set of front solder balls are electrically coupled to the first-type solder balls of the set of rear solder balls.

公开(公告)号：US20250006585A1

公开(公告)日：2025-01-02

申请号：US18740630

申请日：2024-06-12

Applicant: JCET Management Co., Ltd. ,  STATS ChipPAC Pte. Ltd.

Inventor： Zhan YING ,  Kai LIU ,  Yaqin WANG

IPC: H01L23/373 ,  H01L23/00 ,  H01L25/18 ,  H10B80/00

Abstract: A semiconductor package comprises: a package substrate having a front surface and a rear surface, wherein the package substrate comprises: a plurality sets of front conductive patterns; a plurality sets of rear conductive patterns; and a plurality sets of interconnects electrically coupling the set of front conductive patterns with the set of rear conductive patterns, respectively; wherein the package substrate at least comprises a first thermal performance region and a second thermal performance region, wherein the first thermal performance region and the second thermal performance region have different thermal performances; a plurality sets of conductive components attached to the front surface and the rear surface of the package substrate and connected to the plurality sets of front conductive patterns and the plurality sets of rear conductive patterns, wherein the plurality sets of conductive components comprise: a set of first-type conductive components mounted to the first thermal performance region of the package substrate; and a set of second-type conductive components mounted to the second thermal performance region of the package substrate.