公开(公告)号：US09685376B2

公开(公告)日：2017-06-20

申请号：US14801437

申请日：2015-07-16

Applicant: J-DEVICES CORPORATION

Inventor： Yoshihiko Ikemoto ,  Hiroshi Inoue ,  Kiminori Ishido ,  Hiroaki Matsubara ,  Yukari Imaizumi

IPC: H01L23/24 ,  H01L21/44 ,  H01L21/78 ,  H01L23/00

CPC classification number: H01L21/78 ,  H01L21/6835 ,  H01L23/3128 ,  H01L23/562 ,  H01L24/19 ,  H01L25/0657 ,  H01L2221/68318 ,  H01L2221/68327 ,  H01L2221/68372 ,  H01L2221/68381 ,  H01L2224/04105 ,  H01L2224/12105 ,  H01L2224/32225 ,  H01L2224/32245 ,  H01L2224/73267 ,  H01L2224/97 ,  H01L2225/06524 ,  H01L2225/06565 ,  H01L2225/06586 ,  H01L2224/83

Abstract: A semiconductor device including: a support plate 1; a semiconductor chip 2 mounted on one principal surface of the support plate 1 via an adhesive layer, with the element circuit surface of the chip being directed upward; an insulation material layer 4 that seals the semiconductor chip 2 and the periphery of the semiconductor chip; openings formed on an electrode arranged on the element circuit surface of the semiconductor chip 2 in the insulation material layer 4; conductive portions 6 formed in the openings so as to be connected to the electrode of the semiconductor chip; a wiring layer 5 formed on the insulation material layer 4 so as to be connected to the conductive portions 6 and partially extending to the peripheral region of the semiconductor chip 2; and external electrodes 7 formed on the wiring layer 5.