公开(公告)号：US20170308468A1

公开(公告)日：2017-10-26

申请号：US15644280

申请日：2017-07-07

Applicant: International Business Machines Corporation

Inventor： Robert H. Bell, JR. ,  Men-Chow Chiang ,  Hong L. Hua ,  Mysore S. Srinivas

IPC: G06F12/084 ,  G06F12/0855 ,  G06F12/0897 ,  G06F12/0886

CPC classification number: G06F12/084 ,  G06F12/0855 ,  G06F12/0886 ,  G06F12/0897

Abstract: A system and technique for cache line memory access includes a processor, a sectored cache, a memory, a memory controller, and logic. The logic is executable to, responsive to a miss in the cache of a sector address requested by the processor, request a cache line from the memory. The cache line request is divided into first and second cache subline requests. A determination is made as to which of the first and second cache subline requests corresponds to the requested sector address. Responsive to determining that the first cache subline request corresponds to the requested sector address, the first cache subline request is placed into a high priority queue of the memory controller and the second cache subline request is placed into a low priority queue of the memory controller. Requests from the high priority queue are serviced before requests from the low priority queue.

公开(公告)号：US09727469B2

公开(公告)日：2017-08-08

申请号：US13767916

申请日：2013-02-15

Applicant: International Business Machines Corporation

Inventor： Robert H. Bell, Jr. ,  Men-Chow Chiang ,  Hong L. Hua ,  Mysore S. Srinivas

IPC: G06F12/08 ,  G06F12/084 ,  G06F12/0855 ,  G06F12/0886 ,  G06F12/0897

CPC classification number: G06F12/084 ,  G06F12/0855 ,  G06F12/0886 ,  G06F12/0897

Abstract: According to one aspect of the present disclosure, a method and technique for performance-driven cache line memory access is disclosed. The method includes: receiving, by a memory controller of a data processing system, a request for a cache line; dividing the request into a plurality of cache subline requests, wherein at least one of the cache subline requests comprises a high priority data request and at least one of the cache subline requests comprises a low priority data request; servicing the high priority data request; and delaying servicing of the low priority data request until a low priority condition has been satisfied.

公开(公告)号：US20140095791A1

公开(公告)日：2014-04-03

申请号：US13633893

申请日：2012-10-03

Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATION

Inventor： Robert H. Bell, JR. ,  Men-Chow Chiang ,  Hong L. Hua ,  Mysore S. Srinivas

IPC: G06F12/08

CPC classification number: G06F12/084 ,  G06F12/0855 ,  G06F12/0886 ,  G06F12/0897

Abstract: According to one aspect of the present disclosure a system and technique for performance-driven cache line memory access is disclosed. The system includes: a processor, a cache hierarchy coupled to the processor, and a memory coupled to the cache hierarchy. The system also includes logic executable to, responsive to receiving a request for a cache line: divide the request into a plurality of cache subline requests, wherein at least one of the cache subline requests comprises a high priority data request and at least one of the cache subline requests comprises a low priority data request; service the high priority data request; and delay servicing of the low priority data request until a low priority condition has been satisfied.

Abstract translation: 根据本公开的一个方面，公开了一种用于性能驱动的高速缓存行存储器访问的系统和技术。 该系统包括：处理器，耦合到处理器的高速缓存分级以及耦合到高速缓存层级的存储器。 该系统还包括可执行以响应于接收对高速缓存行的请求的逻辑：将该请求划分成多个高速缓存子线请求，其中高速缓存子线请求中的至少一个包括高优先级数据请求，并且至少一个 缓存子线请求包括低优先级数据请求; 服务高优先级数据请求; 以及对低优先级数据请求的延迟服务，直到满足低优先级条件。

公开(公告)号：US09626294B2

公开(公告)日：2017-04-18

申请号：US13633893

申请日：2012-10-03

Applicant: International Business Machines Corporation

Inventor： Robert H. Bell, Jr. ,  Men-Chow Chiang ,  Hong L. Hua ,  Mysore S. Srinivas

IPC: G06F12/08 ,  G06F12/084 ,  G06F12/0855 ,  G06F12/0886 ,  G06F12/0897

CPC classification number: G06F12/084 ,  G06F12/0855 ,  G06F12/0886 ,  G06F12/0897

Abstract: According to one aspect of the present disclosure a system and technique for performance-driven cache line memory access is disclosed. The system includes: a processor, a cache hierarchy coupled to the processor, and a memory coupled to the cache hierarchy. The system also includes logic executable to, responsive to receiving, a request for a cache line: divide the request into a plurality of cache subline requests, wherein at least one of the cache subline requests comprises a high priority data request and at least one of the cache subline requests comprises a low priority data request; service the high priority data request; and delay servicing of the low priority data request until a low priority condition has been satisfied.

公开(公告)号：US08959286B2

公开(公告)日：2015-02-17

申请号：US13854484

申请日：2013-04-01

Applicant: International Business Machines Corporation

Inventor： Robert H. Bell, Jr. ,  Men-Chow Chiang ,  Hong L. Hua ,  Mysore S. Srinivas

IPC: G06F12/00 ,  G06F13/00 ,  G06F13/28 ,  G06F17/30 ,  G06F3/06

CPC classification number: G06F17/30082 ,  G06F3/0611 ,  G06F3/064 ,  G06F3/0647 ,  G06F3/0685

Abstract: A storage subsystem combining solid state drive (SSD) and hard disk drive (HDD) technologies provides low access latency and low complexity. Separate free lists are maintained for the SSD and the HDD and blocks of file system data are stored uniquely on either the SSD or the HDD. When a read access is made to the subsystem, if the data is present on the SSD, the data is returned, but if the block is present on the HDD, it is migrated to the SSD and the block on the HDD is returned to the HDD free list. On a write access, if the block is present in the either the SSD or HDD, the block is overwritten, but if the block is not present in the subsystem, the block is written to the HDD.

Abstract translation: 组合固态硬盘（SSD）和硬盘驱动器（HDD）技术的存储子系统提供低访问延迟和低复杂度。 为SSD保留独立的免费列表，HDD和文件系统数据块可以唯一存储在SSD或HDD上。 当对子系统进行读取访问时，如果SSD上存在数据，则返回数据，但是如果该块存在于HDD上，则迁移到SSD，并将HDD上的块返回到 硬盘免费列表。 在写访问中，如果该块存在于SSD或HDD中，则该块被覆盖，但是如果块不存在于子系统中，则该块被写入HDD。

公开(公告)号：US09378069B2

公开(公告)日：2016-06-28

申请号：US14197581

申请日：2014-03-05

Applicant: International Business Machines Corporation

Inventor： Men-Chow Chiang ,  Ken V. Vu

IPC: G06F9/46 ,  G06F9/52

CPC classification number: G06F9/526 ,  G06F9/4856

Abstract: A method, system and computer-usable medium are disclosed for a lock-spin-wait operation for managing multi-threaded applications in a multi-core computing environment. A target processor core, referred to as a “spin-wait core” (SWC), is assigned (or reserved) for primarily running spin-waiting threads. Threads operating in the multi-core computing environment that are identified as spin-waiting are then moved to a run queue associated with the SWC to acquire a lock. The spin-waiting threads are then allocated a lock response time that is less than the default lock response time of the operating system (OS) associated with the SWC. If a spin-waiting fails to acquire a lock within the allocated lock response time, the SWC is relinquished, ceding its availability for other spin-waiting threads in the run queue to acquire a lock. Once a spin-waiting thread acquires a lock, it is migrated to its original, or an available, processor core.

Abstract translation: 公开了用于在多核计算环境中管理多线程应用程序的锁 - 旋转等待操作的方法，系统和计算机可用介质。 被称为“自旋等待核心”（SWC）的目标处理器核心被分配（或保留）用于主要运行的旋转等待线程。 在多核心计算环境中运行的被识别为自转等待的线程随后被移动到与SWC相关联的运行队列以获取锁定。 然后，旋转等待线程被分配的锁响应时间小于与SWC相关联的操作系统（OS）的默认锁响应时间。 如果自动等待无法在分配的锁定响应时间内获取锁定，则SWC将被放弃，将其在运行队列中的其他旋转等待线程的可用性取消锁定。 一旦旋转等待线程获取锁定，它将迁移到其原始处理器核心或可用的处理器核心。

公开(公告)号：US20140095796A1

公开(公告)日：2014-04-03

申请号：US13767916

申请日：2013-02-15

Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATION

Inventor： Robert H. Bell, JR. ,  Men-Chow Chiang ,  Hong L. Hua ,  Mysore S. Srinivas

IPC: G06F12/08

CPC classification number: G06F12/084 ,  G06F12/0855 ,  G06F12/0886 ,  G06F12/0897

Abstract: According to one aspect of the present disclosure, a method and technique for performance-driven cache line memory access is disclosed. The method includes: receiving, by a memory controller of a data processing system, a request for a cache line; dividing the request into a plurality of cache subline requests, wherein at least one of the cache subline requests comprises a high priority data request and at least one of the cache subline requests comprises a low priority data request; servicing the high priority data request; and delaying servicing of the low priority data request until a low priority condition has been satisfied.

Abstract translation: 根据本公开的一个方面，公开了一种用于性能驱动的高速缓存行存储器访问的方法和技术。 该方法包括：由数据处理系统的存储器控​​制器接收对高速缓存行的请求; 将所述请求划分为多个高速缓存子线请求，其中所述高速缓存子线请求中的至少一个包括高优先级数据请求，并且所述高速缓存子线请求中的至少一个包括低优先级数据请求; 服务高优先级数据请求; 并延迟低优先级数据请求的服务，直到满足低优先级条件。

公开(公告)号：US20130218892A1

公开(公告)日：2013-08-22

申请号：US13854484

申请日：2013-04-01

Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATION

Inventor： Robert H. Bell, JR. ,  Men-Chow Chiang ,  Hong L. Hua ,  Mysore S. Srinivas

IPC: G06F17/30

CPC classification number: G06F17/30082 ,  G06F3/0611 ,  G06F3/064 ,  G06F3/0647 ,  G06F3/0685

Abstract: A storage subsystem combining solid state drive (SSD) and hard disk drive (HDD) technologies provides low access latency and low complexity. Separate free lists are maintained for the SSD and the HDD and blocks of file system data are stored uniquely on either the SSD or the HDD. When a read access is made to the subsystem, if the data is present on the SSD, the data is returned, but if the block is present on the HDD, it is migrated to the SSD and the block on the HDD is returned to the HDD free list. On a write access, if the block is present in the either the SSD or HDD, the block is overwritten, but if the block is not present in the subsystem, the block is written to the HDD.

Abstract translation: 组合固态硬盘（SSD）和硬盘驱动器（HDD）技术的存储子系统提供低访问延迟和低复杂度。 为SSD保留独立的免费列表，HDD和文件系统数据块可以唯一存储在SSD或HDD上。 当对子系统进行读取访问时，如果SSD上存在数据，则返回数据，但是如果该块存在于HDD上，则迁移到SSD，并将HDD上的块返回到 硬盘免费列表。 在写访问中，如果该块存在于SSD或HDD中，则该块被覆盖，但是如果块不存在于子系统中，则该块被写入HDD。