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    Path searcher using reconfigurable correlator sets
    1.
    发明申请
    Path searcher using reconfigurable correlator sets 失效
    路径搜索器使用可重构相关器集

    公开(公告)号：US20040047439A1

    公开(公告)日：2004-03-11

    申请号：US10412475

    申请日：2003-04-11

    Applicant: InterDigital Technology Corporation

    Inventor： John David Kaewell JR. ,  Timothy Berghuis ,  Jan Meyer ,  Peter Bohnhoff ,  Alexander Reznik ,  Edward L. Hepler ,  Michael Koch ,  William C. Hackett ,  David S. Bass ,  Steven Ferrante

    IPC: H04B001/10

    CPC classification number: H04B1/7093 ,  H04B1/7075 ,  H04B1/7077 ,  H04B1/709 ,  H04B1/7113 ,  H04B1/7117 ,  H04B1/712 ,  H04B7/0491 ,  H04B2201/7071 ,  H04B2201/70711

    Abstract: A Node-B/base station has a path searcher and at least one antenna for receiving signals from users. The path searcher comprises a set of correlators. Each correlator correlates an inputted user code with an inputted antenna output of the at least one antenna. An antenna controller selectively couples any output of the at least one antenna to an input of each correlator of the set of correlators. A code phase controller selects a user code for input into the set of correlators. Each delay of a series of delays delays the selected user code by a predetermined amount and each correlator of the set of correlators receives a different code phase delay of the selected user code. A sorter and path selector sorts the output energy levels of each correlator of the sets of correlators and produces a path profile for a user based on the sorted output energy levels.

    Abstract translation: 节点B /基站具有路径搜索器和用于从用户接收信号的至少一个天线。 路径搜索器包括一组相关器。 每个相关器将输入的用户代码与至少一个天线的输入的天线输出相关联。 天线控制器选择性地将至少一个天线的任何输出耦合到该组相关器的每个相关器的输入端。 代码相位控制器选择用于输入到该组相关器的用户代码。 一系列延迟的每个延迟将所选择的用户码延迟预定量，并且该组相关器的每个相关器接收所选用户码的不同码相位延迟。 分拣机和路径选择器对相关器组的每个相关器的输出能量进行排序，并且基于排序的输出能级产生用户的路径简档。

    Enhanced rake structure
    5.
    发明申请
    Enhanced rake structure 有权

    公开(公告)号：US20040170220A1

    公开(公告)日：2004-09-02

    申请号：US10793025

    申请日：2004-03-04

    Applicant: InterDigital Technology Corporation

    Inventor： William C. Hackett

    IPC: H04B001/707

    CPC classification number: H04B1/7117 ,  H04B2201/70707

    Abstract: A rake architecture for a frequency division duplex (FDD) and use also in TDD and TD-SCDMA type communications system, designed to significantly reduce the memory capacity required and thereby also reduce an area on the die of an application specific integrated circuit (ASIC) into which the memory is integrated. A single circular buffer, preferably of the shared memory type is shared by all of the rake fingers of a rake receiver to significantly reduce the hardware and software required to time align multipath signals received by a UE from a base station. This unique time alignment technique also reduces the number of code generators required to track a plurality (typically three) of base stations.

    Enhanced rake structure
    6.
    发明申请
    Enhanced rake structure 失效
    增强耙结构

    公开(公告)号：US20030123528A1

    公开(公告)日：2003-07-03

    申请号：US10034874

    申请日：2001-12-27

    Applicant: InterDigital Technology Corporation

    Inventor： William C. Hackett

    IPC: H04B001/69 ,  H04B001/707

    CPC classification number: H04B1/7117 ,  H04B2201/70707

    Abstract: A rake architecture for a frequency division duplex (FDD) and use also in TDD and TD-SCDMA type communications system, designed to significantly reduce the memory capacity required and thereby also reduce an area on the die of an application specific integrated circuit (ASIC) into which the memory is integrated. A single circular buffer, preferably of the shared memory type is shared by all of the rake fingers of a rake receiver to significantly reduce the hardware and software required to time align multipath signals received by a UE from a base station. This unique time alignment technique also reduces the number of code generators required to track a plurality (typically three) of base stations.

    Abstract translation: 用于频分双工（FDD）的耙式架构，并且还用于TDD和TD-SCDMA型通信系统，旨在显着地减少所需的存储器容量，从而也减少专用集成电路（ASIC）的芯片上的面积， 内存被集成到其中。 优选共享存储器类型的单个循环缓冲器由耙式接收器的所有耙指共享，以显着地减少时间校准由UE从基站接收的多路径信号所需的硬件和软件。 这种独特的时间对准技术还减少了跟踪多个（通常为三个）基站所需的代码生成器的数量。

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