公开(公告)号：US20210021272A1

公开(公告)日：2021-01-21

申请号：US16766921

申请日：2018-03-30

Applicant: Intel IP Corporation

Inventor： Niranjan Karandikar ,  Wayne Ballantyne ,  Gregory Chance ,  Simon Hughes ,  Daniel Schwartz ,  Nebil Tanzi

IPC: H03L7/099 ,  H03L7/093 ,  H03L7/091 ,  H03L7/185

Abstract: Techniques are provided for reducing or mitigating phase noise of a digital phase lock loop or the system depending on the digital phase lock loop. In an example, a multiple-mode digital phase lock loop can include a digital phase lock loop (DPLL), multiple frequency scalers configured to receive a reference clock, and a multiplexer configured to receive a mode command signal and to couple an output of one of the multiple frequency scalers to an input of the DPLL in response to a state of the mode command signal.