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公开(公告)号:US10206191B2
公开(公告)日:2019-02-12
申请号:US15354010
申请日:2016-11-17
Applicant: Intel IP Corporation
Inventor: Siegfried Baer , Pouyan Parvazi
Abstract: A circuit arrangement for determining a mobile radio cell timing is provided. The circuit arrangement may include a receiver configured to receive a paging signal in accordance with a predetermined cell timing, and one or more synchronization signals, a receiver activating/deactivating circuit configured to activate the receiver for a predetermined time period to receive the paging signal in accordance with a previous paging signal cycle, and further configured to deactivate the receiver after the predetermined time period has lapsed, a cell detection circuit configured to execute during the predetermined time period a cell detection procedure using the one or more synchronization signals, thereby determining an updated cell timing, and a memory configured to store the updated cell timing.
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公开(公告)号:US09877270B2
公开(公告)日:2018-01-23
申请号:US15079119
申请日:2016-03-24
Applicant: Intel IP Corporation
Inventor: Matthew Hayes , Tianyan Pu , Pouyan Parvazi
CPC classification number: H04W48/14 , H04W4/00 , H04W48/16 , H04W56/0015
Abstract: A mobile communication device may include a cell search circuit configured to process a first block of signal waveform data to extract a first discrete parameter set, wherein the first discrete parameter set identifies one or more first potential cells present in the first block of signal waveform data, process the second block of signal waveform data to extract a second discrete parameter set, wherein the second discrete parameter set identifies one or more second potential cells present in the second block of signal waveform data, and compare the first discrete parameter set and the second discrete parameter set to identify one or more matching cells, and an RF transceiver configured to transmit or receive radio signals based on the identification of the one or more matching cells.
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公开(公告)号:US09820272B1
公开(公告)日:2017-11-14
申请号:US15183866
申请日:2016-06-16
Applicant: Intel IP Corporation
Inventor: Pouyan Parvazi , Tianyan Pu
CPC classification number: H04W72/042 , H04B7/2615 , H04J11/0069 , H04J11/0073 , H04J11/0076 , H04J11/0089 , H04L5/0094 , H04L5/14 , H04L27/2662 , H04W48/16 , H04W56/00 , H04W84/12
Abstract: A circuit arrangement may include a first detection circuit configured to evaluate signal data of a carrier channel to identify a timing location of a synchronization signal within the signal data, a second detection circuit configured to, using the timing location as a reference point, extract a first candidate synchronization signal from a first candidate timing location of the signal data and to extract a second candidate synchronization signal from a second candidate timing location of the signal data, and a decision circuit configured to analyze the first detection synchronization signal and the second candidate synchronization signal to determine a duplex mode of the carrier channel.
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