公开(公告)号：US20190052452A1

公开(公告)日：2019-02-14

申请号：US16076710

申请日：2017-01-26

Applicant: Intel IP Corporation

Inventor： Uri PERLMUTTER ,  Michael KERNER ,  Uri PARKER

IPC: H04L7/00 ,  H03L7/081 ,  H03L7/093 ,  H04L7/033

Abstract: The present disclosure relates to methods and apparatuses for compensating carrier or clock signal phase fluctuations. An apparatus comprises a digital phase locked loop (210) comprising a phase error output (214) for a phase error (216) between a reference signal (218) and an output signal (212) generated by the digital phase locked loop, and a phase rotator (220) coupled to the phase error output (214) and configured to rotate a phase of a data signal based on the phase error (216).