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公开(公告)号：US20160094249A1
公开(公告)日：2016-03-31
申请号：US14835851
申请日：2015-08-26
Applicant: Intel IP Corporation
Inventor： Ashkan Naeini , Gerhard Mitteregger , Zdravko Boos
CPC classification number: H04B1/0053 , H04B1/0021 , H04B1/006 , H04L5/001 , H04L5/143 , H04L27/0002 , H04L27/261 , H04L27/362 , H04L27/38
Abstract: An apparatus for generating base band receive signals includes a first analog-to-digital converter module generating a first digital high frequency receive signal at least by sampling a first analog high frequency receive signal, a first digital signal processing module generating a first base band receive signal based on the first digital high frequency receive signal, a second analog-to-digital converter module generating a second digital high frequency receive signal at least by sampling a second analog high frequency receive signal and a second digital signal processing module generating a second base band receive signal based on the second digital high frequency receive signal. The first analog high frequency receive signal comprises first payload data at a first receive channel associated with a first carrier frequency and the second analog high frequency receive signal comprises second payload data at a second receive channel associated with a second carrier frequency.
Abstract translation: 用于产生基带接收信号的装置包括：第一模数转换器模块，至少通过对第一模拟高频接收信号进行采样来产生第一数字高频接收信号;第一数字信号处理模块，产生第一基带接收 基于第一数字高频接收信号的信号;第二模数转换器模块，至少通过采样第二模拟高频接收信号产生第二数字高频接收信号;以及第二数字信号处理模块，产生第二基极 基于第二数字高频接收信号的频带接收信号。 第一模拟高频接收信号包括与第一载波频率相关联的第一接收信道的第一有效载荷数据，并且第二模拟高频接收信号包括与第二载波频率相关联的第二接收信道的第二有效载荷数据。
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公开(公告)号：US09608672B2
公开(公告)日：2017-03-28
申请号：US14835851
申请日：2015-08-26
Applicant: Intel IP Corporation
Inventor： Ashkan Naeini , Gerhard Mitteregger , Zdravko Boos
CPC classification number: H04B1/0053 , H04B1/0021 , H04B1/006 , H04L5/001 , H04L5/143 , H04L27/0002 , H04L27/261 , H04L27/362 , H04L27/38
Abstract: An apparatus for generating base band receive signals includes a first analog-to-digital converter module generating a first digital high frequency receive signal at least by sampling a first analog high frequency receive signal, a first digital signal processing module generating a first base band receive signal based on the first digital high frequency receive signal, a second analog-to-digital converter module generating a second digital high frequency receive signal at least by sampling a second analog high frequency receive signal and a second digital signal processing module generating a second base band receive signal based on the second digital high frequency receive signal. The first analog high frequency receive signal comprises first payload data at a first receive channel associated with a first carrier frequency and the second analog high frequency receive signal comprises second payload data at a second receive channel associated with a second carrier frequency.
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