公开(公告)号：US20200310994A1

公开(公告)日：2020-10-01

申请号：US16370928

申请日：2019-03-30

Applicant: Intel Corporation

Inventor： Kermin ChoFleming ,  Yu Bai ,  Simon C. Steely

IPC: G06F13/16 ,  G06F12/0806 ,  G06F16/901

Abstract: Systems, methods, and apparatuses relating to memory interface circuit allocation in a configurable spatial accelerator are described. In one embodiment, a configurable spatial accelerator (CSA) includes a plurality of processing elements; a plurality of request address file (RAF) circuits, and a circuit switched interconnect network between the plurality of processing elements and the RAF circuits. As a dataflow architecture, embodiments of CSA have a unique memory architecture where memory accesses are decoupled into an explicit request and response phase allowing pipelining through memory. Certain embodiments herein provide for an improved memory sub-system design via the improvements to allocation discussed herein.

公开(公告)号：US11249683B2

公开(公告)日：2022-02-15

申请号：US16818637

申请日：2020-03-13

Applicant: Intel Corporation

Inventor： Yu Bai ,  Kermin Chofleming

IPC: G06F3/06

Abstract: Systems, apparatuses and methods may provide for technology that determines a plurality of memory operations associated with a data-flow graph that represents a computer code, where a spatial architecture executes the data-flow graph and the spatial architecture includes a plurality of memory controllers, randomly assigns one or more of the plurality of memory operations to one or more of the plurality of memory controllers to generate a first allocation of the plurality of memory operations to the memory controllers, and determines that the first allocation is to be stored as a permanent memory allocation based on a first performance metric associated with the first allocation.

公开(公告)号：US20200210113A1

公开(公告)日：2020-07-02

申请号：US16818637

申请日：2020-03-13

Applicant: Intel Corporation

Inventor： Yu Bai ,  Kermin Chofleming

IPC: G06F3/06

Abstract: Systems, apparatuses and methods may provide for technology that determines a plurality of memory operations associated with a data-flow graph that represents a computer code, where a spatial architecture executes the data-flow graph and the spatial architecture includes a plurality of memory controllers, randomly assigns one or more of the plurality of memory operations to one or more of the plurality of memory controllers to generate a first allocation of the plurality of memory operations to the memory controllers, and determines that the first allocation is to be stored as a permanent memory allocation based on a first performance metric associated with the first allocation.

公开(公告)号：US20220405209A1

公开(公告)日：2022-12-22

申请号：US17352628

申请日：2021-06-21

Applicant: Intel Corporation

Inventor： Kermin ChoFleming ,  Yu Bai ,  Ping Zou

IPC: G06F12/0895 ,  G06F12/0853 ,  G06F12/0811 ,  G06F12/02

Abstract: An embodiment of an integrated circuit comprises circuitry to generate a cache tag for data to be stored in a cache memory, store a first portion of the cache tag in a primary tag memory, and store a second portion of the cache tag in a secondary tag memory, wherein a size of the first portion is smaller than a size of the second portion. Other embodiments are disclosed and claimed.

公开(公告)号：US10915471B2

公开(公告)日：2021-02-09

申请号：US16370928

申请日：2019-03-30

Applicant: Intel Corporation

Inventor： Kermin ChoFleming ,  Yu Bai ,  Simon C. Steely

IPC: G06F13/16 ,  G06F16/901 ,  G06F12/0806

Abstract: Systems, methods, and apparatuses relating to memory interface circuit allocation in a configurable spatial accelerator are described. In one embodiment, a configurable spatial accelerator (CSA) includes a plurality of processing elements; a plurality of request address file (RAF) circuits, and a circuit switched interconnect network between the plurality of processing elements and the RAF circuits. As a dataflow architecture, embodiments of CSA have a unique memory architecture where memory accesses are decoupled into an explicit request and response phase allowing pipelining through memory. Certain embodiments herein provide for an improved memory sub-system design via the improvements to allocation discussed herein.