公开(公告)号：US20230042495A1

公开(公告)日：2023-02-09

申请号：US17967037

申请日：2022-10-17

Applicant: Intel Corporation

Inventor： Min Liu ,  Young Xiangguo Guo ,  Lei Zhu ,  Yannan Sun ,  Xiang Li

IPC: G06F3/06

Abstract: In coarse memory training approaches, a multiple of a base timing interval is used to reduce the sampling time in a sweep sampling approach during memory training to determine the timing offset between a non-clock memory signal and a memory clock to ensure reliable memory operation at high frequencies. In a hierarchical memory training method, a coarse memory training step is employed to determine adjustable timing offsets where a memory captures the rising and falling edges of a non-clock memory signal and those adjustable timing offsets are used in a subsequent fine memory training step to refine the timing offsets where the memory captures the rising and falling edges of the non-clock memory signal. The hierarchical approach can determine timing offsets for non-clock memory signals with the accuracy of existing (non-coarse, non-hierarchical) memory training methods in less time than the existing methods.