公开(公告)号：US20190042095A1

公开(公告)日：2019-02-07

申请号：US16111156

申请日：2018-08-23

Applicant: Intel Corporation

Inventor： George VERGIS ,  Bill NALE ,  Derek A. THOMPSON ,  James A. McCALL ,  Rajat AGARWAL ,  Wei P. CHEN

IPC: G06F3/06

Abstract: An apparatus is described. The apparatus includes a memory controller having register space to inform the memory controller that the memory controller is coupled to a memory module that conforms to a first memory chip industry standard specification but is composed of memory chips that conform to a second, different memory chip industry standard specification.

公开(公告)号：US20200027500A1

公开(公告)日：2020-01-23

申请号：US16584724

申请日：2019-09-26

Applicant: Intel Corporation

Inventor： Douglas HEYMANN ,  Wei P. CHEN ,  Suresh CHITTOR ,  George VERGIS

IPC: G11C11/406 ,  G06F13/16 ,  G01K13/00

Abstract: Power consumption for refresh of memory devices on a memory module is reduced by each memory device on the memory module to one of a plurality of sub channels on the memory module. Each sub channel has a thermal sensor that monitors the temperature of the DRAM chips in the region. The refresh rate is increased only for the memory devices in the sub channel in which the memory devices operate above a predefined high temperature. This results in a reduction in power required by the memory module for refresh and an increase in the maximum bandwidth of the memory module.

公开(公告)号：US20220229575A1

公开(公告)日：2022-07-21

申请号：US17710796

申请日：2022-03-31

Applicant: Intel Corporation

Inventor： Wei P. CHEN ,  Andrew M. RUDOFF ,  Rajat AGARWAL

IPC: G06F3/06

Abstract: A system can dynamically migrate memory pages from near memory to far memory during runtime. A system basic input output system (BIOS) can program a first memory address space of size P and a second memory address space of size P to a near memory (NM) space of size (N) and a far memory (FM) space of size (M), where P equals N+M. For the first memory address space, the OS can manage the NM space and the FM space as a flat memory space with an address space of size P available. For the second memory address space, the OS can manage the NM space as a NM cache for FM, with an address space of size M available.

公开(公告)号：US20210141692A1

公开(公告)日：2021-05-13

申请号：US17156399

申请日：2021-01-22

Applicant: Intel Corporation

Inventor： Rajat AGARWAL ,  Wei P. CHEN ,  Bill NALE ,  James A. McCALL

IPC: G06F11/10

Abstract: A memory subsystem includes multiple memory resources connected in parallel, including a first memory resource and a second memory resource. The memory subsystem can split a portion of data into multiple sub-portions. Split into smaller portions, the system needs fewer ECC (error checking and correction) bits to provide the same level of ECC protection. The portion of data can include N ECC bits for error correction, and the sub-portions can each include a sub-portion of (N−M) ECC bits for error correction. The system can then use M bits of data for non-ECC purposes, such as metadata.

公开(公告)号：US20240061741A1

公开(公告)日：2024-02-22

申请号：US18268956

申请日：2020-12-26

Applicant: Intel Corporation

Inventor： Rajat AGARWAL ,  Hsing-Min CHEN ,  Wei P. CHEN ,  Wei WU ,  Jing LING ,  Kuljit S. BAINS ,  Kjersten E. CRISS ,  Deep K. BUCH ,  Theodros YIGZAW ,  John G. HOLM ,  Andrew M. RUDOFF ,  Vaibhav SINGH ,  Sreenivas MANDAVA

IPC: G06F11/10

CPC classification number: G06F11/10

Abstract: A memory subsystem includes memory devices with space dynamically allocated for improvement of reliability, availability, and serviceability (RAS) in the system. Error checking and correction (ECC) logic detects an error in all or a portion of a memory device. In response to error detection, the system can dynamically perform one or more of: allocate active memory device space for sparing to spare a failed memory segment; write a poison pattern into a failed cacheline to mark it as failed; perform permanent fault detection (PFD) and adjust application of ECC based on PFD detection; or, spare only a portion of a device and leave another portion active, including adjusting ECC based on the spared portion. The error detection can be based on bits of an ECC device, and error correction based on those bits and additional bits stored on the data devices.

公开(公告)号：US20220350500A1

公开(公告)日：2022-11-03

申请号：US17855688

申请日：2022-06-30

Applicant: Intel Corporation

Inventor： Wei P. CHEN ,  Theodros YIGZAW ,  Sarathy JAYAKUMAR ,  Anthony LUCK ,  Deep K. BUCH ,  Rajat AGARWAL ,  Kuljit S. BAINS ,  John G. HOLM ,  Brent CHARTRAND ,  Keith KLAYMAN

IPC: G06F3/06

Abstract: An apparatus is described. The apparatus includes a processor. The processor includes a memory controller to read and write from a memory. The memory controller includes error correction coding (ECC) circuitry to correct errors in data read from the memory. The processor includes register space to track read data error information. The processor includes an embedded controller. The processor includes local memory coupled to the embedded controller. The embedded controller is to read the read data error information and store the read data error information in the local memory.

公开(公告)号：US20220222178A1

公开(公告)日：2022-07-14

申请号：US17710806

申请日：2022-03-31

Applicant: Intel Corporation

Inventor： Rajat AGARWAL ,  Sai Prashanth MURALIDHARA ,  Wei P. CHEN ,  Nishant SINGH ,  Sharada VENKATESWARAN ,  Daniel W. LIU

IPC: G06F12/0811 ,  G06F12/0815

Abstract: A system includes a multilevel memory such as a two level memory (2LM), where a first level memory acts as a cache for the second level memory. A memory controller or cache controller can detect a cache miss in the first level memory for a request for data. Instead of automatically performing a swap, the controller can determine whether to perform a swap based on a swap policy assigned to a memory region associated with the address of the requested data.

公开(公告)号：US20220107866A1

公开(公告)日：2022-04-07

申请号：US17550859

申请日：2021-12-14

Applicant: Intel Corporation

Inventor： Jing LING ,  Wei P. CHEN ,  Rajat AGARWAL

IPC: G06F11/10 ,  G06F11/14

Abstract: A memory controller having an error checking and correction (ECC) circuitry can detect an error in data being read from memory and correct that error with a retry flow. The read data is stored in a read data buffer at the memory controller when the read data is received from memory. Once the ECC circuitry detects an error in the read data, the retry flow enables access to that data from the read data buffer instead of reading the data from memory for the second time. Access to the data from the read data buffer reduces the overall time needed for the correction flow compared to a retry flow that rereads the data from memory.

公开(公告)号：US20210216452A1

公开(公告)日：2021-07-15

申请号：US17214818

申请日：2021-03-27

Applicant: Intel Corporation

Inventor： Sai Prashanth MURALIDHARA ,  Alaa R. ALAMELDEEN ,  Rajat AGARWAL ,  Wei P. CHEN ,  Vivek KOZHIKKOTTU

IPC: G06F12/0802 ,  G06F3/06

Abstract: A two-level main memory in which both volatile memory and persistent memory are exposed to the operating system in a flat manner and data movement and management is performed in cache line granularity is provided. The operating system can allocate pages in the two-level main memory randomly across the first level main memory and the second level main memory in a memory-type agnostic manner, or, in a more intelligent manner by allocating predicted hot pages in first level main memory and predicted cold pages in second level main memory. The cache line granularity movement is performed in a “swap” manner, that is, a hot cache line in the second level main memory is swapped with a cold cache line in first level main memory because data is stored in either first level main memory or second level main memory not in both first level main memory and second level main memory.