公开(公告)号：US09406618B2

公开(公告)日：2016-08-02

申请号：US14305439

申请日：2014-06-16

Applicant: Intel Corporation

Inventor： John S. Guzek ,  Ravi K. Nalla ,  Javier Solo Gonzalez ,  Drew Delaney ,  Suresh Pothukuchi ,  Mohit Mamodia ,  Edward Zarbock ,  Johanna M. Swan

IPC: H01L23/538 ,  H01L23/498 ,  H01L23/48 ,  H01L23/00 ,  H01L25/03 ,  H01L25/065 ,  H01L25/18

CPC classification number: H01L23/5384 ,  H01L23/481 ,  H01L23/49816 ,  H01L23/49827 ,  H01L23/5389 ,  H01L24/24 ,  H01L24/48 ,  H01L24/73 ,  H01L24/82 ,  H01L25/03 ,  H01L25/0657 ,  H01L25/18 ,  H01L2224/16145 ,  H01L2224/16225 ,  H01L2224/24226 ,  H01L2224/48137 ,  H01L2224/48472 ,  H01L2224/73259 ,  H01L2225/06513 ,  H01L2225/06541 ,  H01L2924/00014 ,  H01L2924/01005 ,  H01L2924/01006 ,  H01L2924/01029 ,  H01L2924/01033 ,  H01L2924/01057 ,  H01L2924/014 ,  H01L2924/14 ,  H01L2924/15174 ,  H01L2924/15311 ,  H01L2924/00 ,  H01L2224/45099 ,  H01L2224/45015 ,  H01L2924/207

Abstract: An apparatus includes a coreless substrate with a through-silicon via (TSV) embedded die that is integral to the coreless substrate. The apparatus includes a subsequent die that is coupled to the TSV die and that is disposed above the coreless substrate.

Abstract translation: 一种装置包括具有与无芯基板成一体的贯通硅通孔（TSV）嵌入管芯的无芯基板。 该设备包括连接到TSV管芯并且设置在无芯基板之上的后续管芯。

公开(公告)号：US20230401130A1

公开(公告)日：2023-12-14

申请号：US17840211

申请日：2022-06-14

Applicant: Intel Corporation

Inventor： Rakesh Mehta ,  Hanmanthrao Patli ,  Ivan Herrera Mejia ,  Raj Chandar Rasappan ,  Hagay Spector ,  Renu Patle ,  Fylur Rahman Sathakathulla ,  Ruchira Liyanage ,  Raju Kasturi ,  Fred Steinberg ,  Ananth Gopalakrishnan ,  Satish Venkatesan ,  Pradyumna Reddy Patnam ,  Suresh Pothukuchi ,  Tapan Ganpule ,  Atthar H. Mohammed ,  Altug Koker

IPC: G06F11/22 ,  G06F11/07

CPC classification number: G06F11/2236 ,  G06F11/0721 ,  G06F11/079

Abstract: One embodiment provides an apparatus comprising a circuit board; an active interposer coupled with the circuit board via a debug package, and a graphics processor die coupled with the active interposer via the debug package. The graphics processor die includes graphics processor resources configured to execute instructions for a multi-die system on chip (SoC) device and excludes functionality that is implemented in a separate due of the multi-die SoC. The apparatus includes a field-programmable gate array (FPGA) including hardware logic that is configurable to emulate functionality provided by the separate die of the multi-die SoC device, which enables silicon validation of the graphics processor die separately from other dies of the multi-die SoC.