公开(公告)号：US12051623B2

公开(公告)日：2024-07-30

申请号：US17107717

申请日：2020-11-30

Applicant: Intel Corporation

Inventor： Seyedhamed M Barghi ,  Shyam Benegal Kadali ,  Marvin Y. Paik ,  Sheng-Po Fang ,  Leonard P. Guler ,  Charles H. Wallace ,  James Y. Jeong

IPC: H01L21/768 ,  H01L21/033 ,  H01L21/311

CPC classification number: H01L21/76897 ,  H01L21/0337 ,  H01L21/31144 ,  H01L21/76816

Abstract: Embodiments disclosed herein include methods of patterning a back end of line (BEOL) stack and the resulting structures. In an embodiment a method of patterning a BEOL stack comprises forming a grating over an interlayer dielectric (ILD), and forming a spacer over the grating. In an embodiment, the spacer is etch selective to the grating. In an embodiment, the method further comprises disposing a hardmask over the grating and the spacer, and patterning the hardmask to form an opening in the hardmask. In an embodiment, the method further comprises filling the opening with a plug, removing the hardmask, and etching the spacer. In an embodiment, a portion of the spacer is protected from the etch by the plug. In an embodiment, the method may further comprise removing the plug, and transferring the grating into the ILD with an etching process.