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    Computing apparatus with closed cooling loop
    6.
    发明授权
    Computing apparatus with closed cooling loop 有权

    公开(公告)号：US11026351B2

    公开(公告)日：2021-06-01

    申请号：US15754957

    申请日：2015-09-25

    Applicant: Intel Corporation

    Inventor： Devdatta P. Kulkarni ,  Richard J. Dischler

    IPC: H05K7/20 ,  H05K1/02 ,  H05K1/18

    Abstract: The present disclosure describes embodiments of apparatuses and methods related to a computing apparatus with a closed cooling loop thermally coupled to one or more processors disposed on a circuit board of the computing apparatus. The closed cooling loop circulates a dielectric fluid to absorb heat from the processor. A portion of the dielectric fluid is evaporated from the processor heat absorbed by the dielectric fluid. A heat exchanger is coupled to the circuit board and thermally coupled to the closed cooling loop. The heat exchanger is to include a coolant flow to remove heat from the dielectric fluid circulated through the portion of the closed cooling loop thermally coupled to the heat exchanger. A vapor portion of the dielectric fluid is condensed from the heat removed by the coolant flow. Other embodiments may be described and/or claimed.

    Methods of direct cooling of packaged devices and structures formed thereby
    8.
    发明授权
    Methods of direct cooling of packaged devices and structures formed thereby 有权

    公开(公告)号：US10228735B2

    公开(公告)日：2019-03-12

    申请号：US15637439

    申请日：2017-06-29

    Applicant: Intel Corporation

    Inventor： Devdatta P. Kulkarni ,  Richard J. Dischler ,  Je-Young Chang

    IPC: G06F1/20 ,  H01L21/02 ,  H01L23/367 ,  H01L23/495

    Abstract: Methods of forming microelectronic package structures/modules, and structures formed thereby, are described. Structures formed herein may include a die disposed on a substrate; a cooling solution comprising a first surface and a second surface opposite the first surface, wherein the second surface is disposed on a backside of the die disposed on a package substrate. A lid comprising an outer surface is disposed on the first surface of the cooling solution, wherein the lid includes a plurality of fins disposed on an inner surface of the lid. A solder is disposed between the outer surface of the lid and the first surface of the cooling solution.

    SIGNAL PATHWAYS IN MULTI-TILE PROCESSORS
    9.
    发明申请
    SIGNAL PATHWAYS IN MULTI-TILE PROCESSORS 审中-公开

    公开(公告)号：US20190042534A1

    公开(公告)日：2019-02-07

    申请号：US15980579

    申请日：2018-05-15

    Applicant: Intel Corporation

    Inventor： William J. Butera ,  Simon C. Steely, JR. ,  Richard J. Dischler

    IPC: G06F15/80 ,  G06F9/54

    Abstract: Embodiments herein may present a multi-tile processor including a plurality of processor tiles, and a plurality of interconnects selectively coupling the plurality of processor tiles to each other. A first processor tile may include a memory to store a bulletin board to hold a message, an execution unit, and an encapsulated software module. The encapsulated software module may select a second processor tile coupled with the first processor tile by an interconnect to be a part of a signal pathway. The second processor tile may be selected based on a selection criterion of the signal pathway and the message held in the bulletin board. The encapsulated software module may post and read a message at the bulletin board stored in the memory, or read a message from a bulletin board stored in a memory of the second processor tile. Other embodiments may be described and/or claimed.

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