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公开(公告)号:US20180120347A1
公开(公告)日:2018-05-03
申请号:US15341726
申请日:2016-11-02
Applicant: INTEL CORPORATION
Inventor: Vikas Rao , Navneet K. Singh , Naveen G
CPC classification number: G01R1/0416 , G01R1/07371
Abstract: Disclosed herein is technology of a probe connector for a probing pad structure around a thermal attach mounting hole. A probe connector includes a socket frame including a first channel and an elongated body including a second channel. Socket conductors are disposed in the socket frame around the first channel. The second channel is disposed at a first distal end of the elongated body, and the elongated body is disposed on the socket frame. The socket conductors are to make electrical contact with a probing pad structure disposed on a surface area around a thermal attach mounting hole of a circuit board in response to a loading attachment engaging with the elongated body via the second channel, the socket frame via the first channel, and the circuit board via the thermal attach mounting hole.
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公开(公告)号:US12051976B2
公开(公告)日:2024-07-30
申请号:US17023203
申请日:2020-09-16
Applicant: Intel Corporation
Inventor: Jagadish Vasudeva Singh , Ankur Mishra , Naveen G , Arvind S
IPC: H02M3/158 , H03K17/687
CPC classification number: H02M3/1582 , H03K17/6871
Abstract: A buck-boost converter having dual-folded bootstrap for driver metal oxide semiconductor (DrMOS) device that, in addition to the traditional bootstrap capacitors, include folded bootstrap capacitors that cross-couple inductor nodes to the two sets of DrMOS switches. The DrMOS switches can be n-type or p-type, and can be replaced with driver Gallium Nitride (DrGaN) devices.
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公开(公告)号:US10656177B2
公开(公告)日:2020-05-19
申请号:US16410852
申请日:2019-05-13
Applicant: Intel Corporation
Inventor: Vikas Rao , Navneet K. Singh , Naveen G
Abstract: A system includes a probe connector including first traces coupled to first conductors curvilinearly arranged around a first elongated portion of the probe connector. The system further includes a circuit board including second traces coupled to first connector pads curvilinearly arranged around a first hole in the circuit board. The first connector pads are to couple to the first conductors of the probe connector when the first elongated portion is inserted in the first hole. The system further comprises a first integrated circuit disposed on the circuit board, the first integrated circuit being coupled to the second traces.
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公开(公告)号:US10317428B2
公开(公告)日:2019-06-11
申请号:US15341726
申请日:2016-11-02
Applicant: INTEL CORPORATION
Inventor: Vikas Rao , Navneet K. Singh , Naveen G
Abstract: Disclosed herein is technology of a probe connector for a probing pad structure around a thermal attach mounting hole. A probe connector includes a socket frame including a first channel and an elongated body including a second channel. Socket conductors are disposed in the socket frame around the first channel. The second channel is disposed at a first distal end of the elongated body, and the elongated body is disposed on the socket frame. The socket conductors are to make electrical contact with a probing pad structure disposed on a surface area around a thermal attach mounting hole of a circuit board in response to a loading attachment engaging with the elongated body via the second channel, the socket frame via the first channel, and the circuit board via the thermal attach mounting hole.
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公开(公告)号:US20220085718A1
公开(公告)日:2022-03-17
申请号:US17023203
申请日:2020-09-16
Applicant: Intel Corporation
Inventor: Jagadish Vasudeva Singh , Ankur Mishra , Naveen G , Arvind S
IPC: H02M3/158 , H03K17/687
Abstract: A buck-boost converter having dual-folded bootstrap for driver metal oxide semiconductor (DrMOS) device that, in addition to the traditional bootstrap capacitors, include folded bootstrap capacitors that cross-couple inductor nodes to the two sets of DrMOS switches. The DrMOS switches can be n-type or p-type, and can be replaced with driver Gallium Nitride (DrGaN) devices.
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公开(公告)号:US20210349134A1
公开(公告)日:2021-11-11
申请号:US17109031
申请日:2020-12-01
Applicant: Intel Corporation
Inventor: Sriram Ranganathan , Naveen G , Pannerkumar Rajagopal , Govindaraj Gettimalli , Javahar Ragothaman
IPC: G01R21/133 , G06F1/3246 , G06F1/3234
Abstract: A Power Management Controller (PMC) which manages power states of a platform, informs a power accumulator device to start measuring the platform power during entry into the low power state (e.g., S0iX). The power accumulator device starts measuring the power until a stop message comes from the PMC. The PMC on detection of any wake event initiates a stop message to the power accumulator device. Once an operating system (OS) context is restored, software can read the measured data from the power accumulator device. The measured data is accessible to a host software using standard software application programming interface (API) and can be used to influence the power policies of the system.
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公开(公告)号:US20190271720A1
公开(公告)日:2019-09-05
申请号:US16410852
申请日:2019-05-13
Applicant: Intel Corporation
Inventor: Vikas Rao , Navneet K. Singh , Naveen G
Abstract: A system includes a probe connector including first traces coupled to first conductors curvilinearly arranged around a first elongated portion of the probe connector. The system further includes a circuit board including second traces coupled to first connector pads curvilinearly arranged around a first hole in the circuit board. The first connector pads are to couple to the first conductors of the probe connector when the first elongated portion is inserted in the first hole. The system further comprises a first integrated circuit disposed on the circuit board, the first integrated circuit being coupled to the second traces.
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公开(公告)号:US20190171269A1
公开(公告)日:2019-06-06
申请号:US16269551
申请日:2019-02-06
Applicant: Intel Corporation
Inventor: Naveen G , Bharath Kumar
Abstract: Technology for a system operable to extend a level of processor performance is disclosed. The system can comprise a power source connected to a platform voltage regulator (VR) and one or more processors and configured to provide an input power to the platform VR. The system can further comprise the platform VR connected to a peripheral interface and the one or more processors and configured to power the peripheral interface and send a power good signal to the one or more processors. The system can further comprise the peripheral interface connected to the platform VR and the one or more processors and configured to connect to a peripheral device and send a signal to the one or more processors when a peripheral interface connection state is identified as connected.
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公开(公告)号:US11422173B2
公开(公告)日:2022-08-23
申请号:US17109031
申请日:2020-12-01
Applicant: Intel Corporation
Inventor: Sriram Ranganathan , Naveen G , Pannerkumar Rajagopal , Govindaraj Gettimalli , Javahar Ragothaman
IPC: G01R21/133 , G06F1/32 , G06F1/3234 , G06F1/3246
Abstract: A Power Management Controller (PMC) which manages power states of a platform, informs a power accumulator device to start measuring the platform power during entry into the low power state (e.g., S0iX). The power accumulator device starts measuring the power until a stop message comes from the PMC. The PMC on detection of any wake event initiates a stop message to the power accumulator device. Once an operating system (OS) context is restored, software can read the measured data from the power accumulator device. The measured data is accessible to a host software using standard software application programming interface (API) and can be used to influence the power policies of the system.
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公开(公告)号:US11327547B2
公开(公告)日:2022-05-10
申请号:US17068704
申请日:2020-10-12
Applicant: Intel Corporation
Inventor: Naveen G , Bharath Kumar
IPC: G06F1/32 , G06F1/26 , G06F1/3206
Abstract: Technology for a system operable to extend a level of processor performance is disclosed. The system can comprise a power source connected to a platform voltage regulator (VR) and one or more processors and configured to provide an input power to the platform VR. The system can further comprise the platform VR connected to a peripheral interface and the one or more processors and configured to power the peripheral interface and send a power good signal to the one or more processors. The system can further comprise the peripheral interface connected to the platform VR and the one or more processors and configured to connect to a peripheral device and send a signal to the one or more processors when a peripheral interface connection state is identified as connected.
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