公开(公告)号：US11158292B2

公开(公告)日：2021-10-26

申请号：US16752427

申请日：2020-01-24

Applicant: Intel Corporation

Inventor： Prashant Chaudhari ,  Arthur Runyan ,  Michael Derr ,  Jonathan Oder

IPC: G09G5/391 ,  G09G5/36 ,  G06F1/08 ,  H03C3/09 ,  H03L7/07

Abstract: Upon external display configuration change, a graphics display driver or any suitable hardware or software modifies the clock frequency of the processor core (e.g., graphics processor core) display engine. The graphics display driver or any suitable hardware or software reprograms the core display clock PLL (CDCLK PLL) to a new frequency, without any dead clocks during such frequency change. A divide-by-2 divider changes the frequency of the PLL on the fly or dynamically. The technique may not require the PLL to be turned off and turned back again at all.

公开(公告)号：US20210233501A1

公开(公告)日：2021-07-29

申请号：US16752427

申请日：2020-01-24

Applicant: Intel Corporation

Inventor： Prashant Chaudhari ,  Arthur Runyan ,  Michael Derr ,  Jonathan Oder

IPC: G09G5/391 ,  G06F1/08 ,  H03C3/09 ,  H03L7/07

Abstract: Upon external display configuration change, a graphics display driver or any suitable hardware or software modifies the clock frequency of the processor core (e.g., graphics processor core) display engine. The graphics display driver or any suitable hardware or software reprograms the core display clock PLL (CDCLK PLL) to a new frequency, without any dead clocks during such frequency change. A divide-by-2 divider changes the frequency of the PLL on the fly or dynamically. The technique may not require the PLL to be turned off and turned back again at all.