公开(公告)号：US20220058853A1

公开(公告)日：2022-02-24

申请号：US17500631

申请日：2021-10-13

Applicant: Intel Corporation

Inventor： HUGUES LABBE ,  DARREL PALKE ,  SHERINE ABDELHAK ,  JILL BOYCE ,  VARGHESE GEORGE ,  SCOTT JANUS ,  ADAM LAKE ,  ZHIJUN LEI ,  ZHENGMIN LI ,  MIKE MACPHERSON ,  CARL MARSHALL ,  SELVAKUMAR PANNEER ,  PRASOONKUMAR SURTI ,  KARTHIK VEERAMANI ,  DEEPAK VEMBAR ,  VALLABHAJOSYULA SRINIVASA SOMAYAZULU

IPC: G06T15/00 ,  G06N3/08 ,  G06T17/20 ,  G06T1/60 ,  G06T15/40 ,  G06T1/20

Abstract: One embodiment provides for a graphics processor comprising a block of graphics compute units, a graphics processor pipeline coupled to the block of graphics compute units, and a programmable neural network unit including one or more neural network hardware blocks. The programmable neural network unit is coupled with the block of graphics compute units and the graphics processor pipeline. The one or more neural network hardware blocks include hardware to perform neural network operations and activation operations for a layer of a neural network. The programmable neural network unit can configure settings of one or more hardware blocks within the graphics processor pipeline based on a machine learning model trained to optimize performance of a set of workloads.

公开(公告)号：US20210150770A1

公开(公告)日：2021-05-20

申请号：US17095544

申请日：2020-11-11

Applicant: Intel Corporation

Inventor： ABHISHEK R. APPU ,  PRASOONKUMAR SURTI ,  JILL BOYCE ,  SUBRAMANIAM MAIYURAN ,  MICHAEL APODACA ,  ADAM T. LAKE ,  JAMES HOLLAND ,  VASANTH RANGANATHAN ,  ALTUG KOKER ,  LIDONG XU ,  NIKOS KABURLASOS

IPC: G06T9/00 ,  G06N3/04 ,  G06T15/00

Abstract: Embodiments described herein provided for an instruction and associated logic to enable a processing resource including a tensor accelerator to perform optimized computation of sparse submatrix operations. One embodiment provides hardware logic to apply a numerical transform to matrix data to increase the sparsity of the data. Increasing the sparsity may result in a higher compression ratio when the matrix data is compressed.

公开(公告)号：US20230421738A1

公开(公告)日：2023-12-28

申请号：US18347278

申请日：2023-07-05

Applicant: Intel Corporation

Inventor： MAYURESH VARERKAR ,  STANLEY BARAN ,  MICHAEL APODACA ,  PRASOONKUMAR SURTI ,  ATSUO KUWAHARA ,  NARAYAN BISWAL ,  JILL BOYCE ,  YI-JEN CHIU ,  GOKCEN CILINGIR ,  BARNAN DAS ,  ATUL DIVEKAR ,  SRIKANTH POTLURI ,  NILESH SHAH ,  ARCHIE SHARMA

IPC: H04N13/111 ,  H04N19/597 ,  G06F9/38 ,  G06F3/01 ,  G06N20/00

CPC classification number: H04N13/111 ,  H04N19/597 ,  G06F9/3877 ,  G06F3/012 ,  G06N20/00

Abstract: A mechanism is described for facilitating adaptive resolution and viewpoint-prediction for immersive media in computing environments. An apparatus of embodiments, as described herein, includes one or more processors to receive viewing positions associated with a user with respect to a display, and analyze relevance of media contents based on the viewing positions, where the media content includes immersive videos of scenes captured by one or more cameras. The one or more processors are further to predict portions of the media contents as relevant portions based on the viewing positions and transmit the relevant portions to be rendered and displayed.

公开(公告)号：US20200051309A1

公开(公告)日：2020-02-13

申请号：US16537140

申请日：2019-08-09

Applicant: Intel Corporation

Inventor： HUGUES LABBE ,  DARREL PALKE ,  SHERINE ABDELHAK ,  JILL BOYCE ,  VARGHESE GEORGE ,  SCOTT JANUS ,  ADAM LAKE ,  ZHIJUN LEI ,  ZHENGMIN LI ,  MIKE MACPHERSON ,  CARL MARSHALL ,  SELVAKUMAR PANNEER ,  PRASOONKUMAR SURTI ,  KARTHIK VEERAMANI ,  DEEPAK VEMBAR ,  VALLABHAJOSYULA SRINIVASA SOMAYAZULU

IPC: G06T15/00 ,  G06N3/08 ,  G06T1/20 ,  G06T1/60 ,  G06T15/40 ,  G06T17/20

Abstract: One embodiment provides for a graphics processor comprising a block of graphics compute units, a graphics processor pipeline coupled to the block of graphics compute units, and a programmable neural network unit including one or more neural network hardware blocks. The programmable neural network unit is coupled with the block of graphics compute units and the graphics processor pipeline. The one or more neural network hardware blocks include hardware to perform neural network operations and activation operations for a layer of a neural network. The programmable neural network unit can configure settings of one or more hardware blocks within the graphics processor pipeline based on a machine learning model trained to optimize performance of a set of workloads.

公开(公告)号：US20220191458A1

公开(公告)日：2022-06-16

申请号：US17562062

申请日：2021-12-27

Applicant: Intel Corporation

Inventor： JILL BOYCE

IPC: H04N13/178 ,  H04N13/398 ,  H04N13/366

Abstract: Embodiments described herein provide for techniques to reduce the complexity of rendering immersive 3D video content. One embodiment provides for an apparatus comprising one or more processors to receive a data set that represents a two-dimensional encoding of planar projections of a frame of a three-dimensional video, decode the two-dimensional encoding into texture data, geometry data, and metadata, determine, based on the metadata, a visibility status and an occupancy status for a sample position in the three-dimensional video, and render video data for the sample position when the sample position is visible and occupied.

公开(公告)号：US20200045285A1

公开(公告)日：2020-02-06

申请号：US16050322

申请日：2018-07-31

Applicant: Intel Corporation

Inventor： MAYURESH VARERKAR ,  STANLEY BARAN ,  MICHAEL APODACA ,  PRASOONKUMAR SURTI ,  ATSUO KUWAHARA ,  NARAYAN BISWAL ,  JILL BOYCE ,  YI-JEN CHIU ,  GOKCEN CILINGIR ,  BARNAN DAS ,  ATUL DIVEKAR ,  SRIKANTH POTLURI ,  NILESH SHAH ,  ARCHIE SHARMA

IPC: H04N13/111 ,  H04N19/597 ,  G06F3/01 ,  G06F9/38 ,  G06F15/18

Abstract: A mechanism is described for facilitating adaptive resolution and viewpoint-prediction for immersive media in computing environments. An apparatus of embodiments, as described herein, includes one or more processors to receive viewing positions associated with a user with respect to a display, and analyze relevance of media contents based on the viewing positions, where the media content includes immersive videos of scenes captured by one or more cameras. The one or more processors are further to predict portions of the media contents as relevant portions based on the viewing positions and transmit the relevant portions to be rendered and displayed.

公开(公告)号：US20230377209A1

公开(公告)日：2023-11-23

申请号：US18322194

申请日：2023-05-23

Applicant: Intel Corporation

Inventor： ABHISHEK R. APPU ,  PRASOONKUMAR SURTI ,  JILL BOYCE ,  SUBRAMANIAM MAIYURAN ,  MICHAEL APODACA ,  ADAM T. LAKE ,  JAMES HOLLAND ,  VASANTH RANGANATHAN ,  ALTUG KOKER ,  LIDONG XU ,  NIKOS KABURLASOS

IPC: G06T9/00 ,  G06T15/00 ,  G06N3/045

CPC classification number: G06T9/002 ,  G06T9/007 ,  G06T15/005 ,  G06T9/008 ,  G06N3/045

Abstract: Embodiments described herein provided for an instruction and associated logic to enable a processing resource including a tensor accelerator to perform optimized computation of sparse submatrix operations. One embodiment provides a parallel processor comprising a processing cluster coupled with the cache memory. The processing cluster includes a plurality of multiprocessors coupled with a data interconnect, where a multiprocessor of the plurality of multiprocessors includes a tensor core configured to load tensor data and metadata associated with the tensor data from the cache memory, wherein the metadata indicates a first numerical transform applied to the tensor data, perform an inverse transform of the first numerical transform, perform a tensor operation on the tensor data after the inverse transform is performed, and write output of the tensor operation to a memory coupled with the processing cluster.

公开(公告)号：US20230360307A1

公开(公告)日：2023-11-09

申请号：US18310015

申请日：2023-05-01

Applicant: Intel Corporation

Inventor： HUGUES LABBE ,  DARREL PALKE ,  SHERINE ABDELHAK ,  JILL BOYCE ,  VARGHESE GEORGE ,  SCOTT JANUS ,  ADAM LAKE ,  ZHIJUN LEI ,  ZHENGMIN LI ,  MIKE MACPHERSON ,  CARL MARSHALL ,  SELVAKUMAR PANNEER ,  PRASOONKUMAR SURTI ,  KARTHIK VEERAMANI ,  DEEPAK VEMBAR ,  VALLABHAJOSYULA SRINIVASA SOMAYAZULU

IPC: G06T15/00 ,  G06N3/08 ,  G06T17/20 ,  G06T1/60 ,  G06T15/40 ,  G06T1/20

CPC classification number: G06T15/005 ,  G06N3/08 ,  G06T17/20 ,  G06T1/60 ,  G06T15/40 ,  G06T1/20

Abstract: One embodiment provides a graphics processor comprising a block of execution resources, a cache memory, a cache memory prefetcher, and circuitry including a programmable neural network unit, the programmable neural network unit comprising a network hardware block including circuitry to perform neural network operations and activation operations for a layer of a neural network, the programmable neural network unit addressable by cores within the block of graphics cores and the neural network hardware block configured to perform operations associated with a neural network configured to determine a prefetch pattern for the cache memory prefetcher.

公开(公告)号：US20220182592A1

公开(公告)日：2022-06-09

申请号：US17526633

申请日：2021-11-15

Applicant: Intel Corporation

Inventor： MAYURESH VARERKAR ,  STANLEY BARAN ,  MICHAEL APODACA ,  PRASOONKUMAR SURTI ,  ATSUO KUWAHARA ,  NARAYAN BISWAL ,  JILL BOYCE ,  YI-JEN CHIU ,  GOKCEN CILINGIR ,  BARNAN DAS ,  ATUL DIVEKAR ,  SRIKANTH POTLURI ,  NILESH SHAH ,  ARCHIE SHARMA

IPC: H04N13/111 ,  H04N19/597 ,  G06F9/38 ,  G06F3/01 ,  G06N20/00

Abstract: A mechanism is described for facilitating adaptive resolution and viewpoint-prediction for immersive media in computing environments. An apparatus of embodiments, as described herein, includes one or more processors to receive viewing positions associated with a user with respect to a display, and analyze relevance of media contents based on the viewing positions, where the media content includes immersive videos of scenes captured by one or more cameras. The one or more processors are further to predict portions of the media contents as relevant portions based on the viewing positions and transmit the relevant portions to be rendered and displayed.

公开(公告)号：US20200043190A1

公开(公告)日：2020-02-06

申请号：US16050724

申请日：2018-07-31

Applicant: Intel Corporation

Inventor： JASON TANNER ,  KAI XIAO ,  JILL BOYCE ,  NARAYAN BISWAL ,  JEFFREY TRIPP

IPC: G06T7/593 ,  G06T7/13 ,  G06T7/136 ,  G06T5/00 ,  G06T15/00 ,  G06T1/20

Abstract: Embodiments described herein provide an apparatus comprising a processor to divide a first image projection into a plurality of regions, the plurality of regions comprising a plurality of points, determine an accuracy rating for the plurality of regions, and apply one of a first rendering technique to a first region in the plurality of regions when the accuracy rating for the first region in the plurality of regions fails to meet an accuracy threshold or a second rendering technique to the first region in the plurality of regions when the accuracy rating for the first region in the plurality of regions meets an accuracy threshold, and a memory communicatively coupled to the processor. Other embodiments may be described and claimed.