公开(公告)号：US11360809B2

公开(公告)日：2022-06-14

申请号：US16024343

申请日：2018-06-29

Applicant: Intel Corporation

Inventor： William Paul Griffin ,  Joshua Fryman ,  Jason Howard ,  Sang Phill Park ,  Robert Pawlowski ,  Michael Abbott ,  Scott Cline ,  Samkit Jain ,  Ankit More ,  Vincent Cave ,  Fabrizio Petrini ,  Ivan Ganev

IPC: G06F9/48 ,  G06F9/38 ,  G06F9/30

Abstract: Embodiments of apparatuses, methods, and systems for scheduling tasks to hardware threads are described. In an embodiment, a processor includes a multiple hardware threads and a task manager. The task manager is to issue a task to a hardware thread. The task manager includes a hardware task queue to store a descriptor for the task. The descriptor is to include a field to store a value to indicate whether the task is a single task, a collection of iterative tasks, and a linked list of tasks.

公开(公告)号：US20240069921A1

公开(公告)日：2024-02-29

申请号：US18477884

申请日：2023-09-29

Applicant: Intel Corporation

Inventor： Scott Cline ,  Robert Pawlowski ,  Joshua Fryman ,  Ivan Ganev ,  Vincent Cave ,  Sebastian Szkoda ,  Fabio Checconi

IPC: G06F9/38 ,  G06F9/30

CPC classification number: G06F9/3885 ,  G06F9/30036

Abstract: Technology described herein provides a dynamically reconfigurable processing core. The technology includes a plurality of pipelines comprising a core, where the core is reconfigurable into one of a plurality of core modes, a core network to provide inter-pipeline connections for the pipelines, and logic to receive a morph instruction including a target core mode from an application running on the core, determine a present core state for the core, and morph, based on the present core state, the core to the target core mode. In embodiments, to morph the core, the logic is to select, based on the target core mode, which inter-pipeline connections are active, where each pipeline includes at least one multiplexor via which the inter-pipeline connections are selected to be active. In embodiments, to morph the core, the logic is further to select, based on the target core mode, which memory access paths are active.

公开(公告)号：US20200004587A1

公开(公告)日：2020-01-02

申请号：US16024343

申请日：2018-06-29

Applicant: Intel Corporation

Inventor： Paul Griffin ,  Joshua Fryman ,  Jason Howard ,  Sang Phill Park ,  Robert Pawlowski ,  Michael Abbott ,  Scott Cline ,  Samkit Jain ,  Ankit More ,  Vincent Cave ,  Fabrizio Petrini ,  Ivan Ganev

IPC: G06F9/48 ,  G06F9/38 ,  G06F9/30

Abstract: Embodiments of apparatuses, methods, and systems for a multithreaded processor core with hardware-assisted task scheduling are described. In an embodiment, a processor includes a first hardware thread, a second hardware thread, and a task manager. The task manager is to issue a task to the first hardware thread. The task manager includes a hardware task queue in which to store a plurality of task descriptors. Each of the task descriptors is to represent one of a single task, a collection of iterative tasks, and a linked list of tasks.