公开(公告)号：US20230089684A1

公开(公告)日：2023-03-23

申请号：US17479369

申请日：2021-09-20

Applicant: Intel Corporation

Inventor： Yosuke Kanaoka ,  Robin Mcree ,  Gang Duan ,  Gautam Medhi ,  Huang-Ta Chen

IPC: H01L23/544

Abstract: A substrate for an electronic device may include one or more layers. The substrate may include a cavity defined in the substrate. The cavity may be adapted to receive a semiconductor die. The substrate may include a fiducial mark positioned proximate the cavity. The fiducial mark may be exposed on a first surface of the substrate. The fiducial mark may include a first region including a dielectric filler material. The fiducial mark may include a second region including a conductive filler material. In an example, the second region surrounds the first region. In another example, the dielectric filler material has a lower reflectivity in comparison to the conductive filler material to provide a contrast between the first region and the second region.

公开(公告)号：US12218063B2

公开(公告)日：2025-02-04

申请号：US16810192

申请日：2020-03-05

Applicant: Intel Corporation

Inventor： Jianyong Xie ,  Sujit Sharan ,  Huang-Ta Chen

IPC: H01L23/538 ,  H01L23/00 ,  H01L23/498 ,  H01L23/64 ,  H01L25/18

Abstract: Embodiments disclosed herein include electronic packages with a bridge that comprise improved power delivery architectures. In an embodiment, a bridge comprises a substrate and a routing stack over the substrate. In an embodiment, the routing stack comprises first routing layers, where individual ones of the first routing layers have a first thickness, and a second routing layer, where the second routing layer has a second thickness that is greater than the first thickness.