公开(公告)号：US20230089684A1

公开(公告)日：2023-03-23

申请号：US17479369

申请日：2021-09-20

Applicant: Intel Corporation

Inventor： Yosuke Kanaoka ,  Robin Mcree ,  Gang Duan ,  Gautam Medhi ,  Huang-Ta Chen

IPC: H01L23/544

Abstract: A substrate for an electronic device may include one or more layers. The substrate may include a cavity defined in the substrate. The cavity may be adapted to receive a semiconductor die. The substrate may include a fiducial mark positioned proximate the cavity. The fiducial mark may be exposed on a first surface of the substrate. The fiducial mark may include a first region including a dielectric filler material. The fiducial mark may include a second region including a conductive filler material. In an example, the second region surrounds the first region. In another example, the dielectric filler material has a lower reflectivity in comparison to the conductive filler material to provide a contrast between the first region and the second region.

公开(公告)号：US20230078395A1

公开(公告)日：2023-03-16

申请号：US17472048

申请日：2021-09-10

Applicant: Intel Corporation

Inventor： Robin Mcree ,  Yosuke Kanaoka ,  Gang Duan ,  Jinhe Liu ,  Timothy A. Gosselin

IPC: H01L23/00 ,  H01L23/31

Abstract: Disclosed herein are embedded heterogeneous architectures having minimized die shift and methods for manufacturing the same. The architectures may include a substrate, a bridge, and a material attached to the substrate. The substrate may include a first subset of vias and a second subset of vias. The bridge may be located in between the first subset and the second subset of vias. The material may include a first portion located proximate the first subset of vias, and a second portion located proximate the second subset of vias. The first and second portions may define a partial boundary of a cavity formed within the substrate and the bridge may be located within the cavity.