公开(公告)号：US20180285151A1

公开(公告)日：2018-10-04

申请号：US15476379

申请日：2017-03-31

Applicant: Intel Corporation

Inventor： Ren Wang ,  Daniel P. Daly ,  Antoine Kaufmann ,  Saikrishna Edupuganti ,  Tsung-Yuan C. Tai

IPC: G06F9/48 ,  G06F11/34 ,  G06F11/30

Abstract: A network interface card (NIC) can be configured to monitor a first central processing unit (CPU) core mapped to a first receive queue having a receive queue length. The NIC can also be configured to determine whether the CPU core is overloaded based on the receive queue length. The NIC can also be configured to redirect data packets that were targeted from the first receive queue to the CPU core to another CPU core responsive to a determination that the CPU core is overloaded.

公开(公告)号：US20210141676A1

公开(公告)日：2021-05-13

申请号：US17152573

申请日：2021-01-19

Applicant: Intel Corporation

Inventor： Ren Wang ,  Daniel P. Daly ,  Antoine Kaufmann ,  Saikrishna Edupuganti ,  Tsung-Yuan C. Tai

IPC: G06F9/50

Abstract: A network interface card (NIC) can be configured to monitor a first central processing unit (CPU) core mapped to a first receive queue having a receive queue length. The NIC can also be configured to determine whether the CPU core is overloaded based on the receive queue length. The NIC can also be configured to redirect data packets that were targeted from the first receive queue to the CPU core to another CPU core responsive to a determination that the CPU core is overloaded.

公开(公告)号：US10073775B2

公开(公告)日：2018-09-11

申请号：US15089035

申请日：2016-04-01

Applicant: Intel Corporation

Inventor： Christopher B. Wilerkson ,  Ren Wang ,  Antoine Kaufmann ,  Anil Vasudevan ,  Robert G. Blankenship ,  Venkata Krishnan ,  Tsung-Yuan C. Tai

IPC: G06F12/00 ,  G06F12/0808 ,  G06F12/0811 ,  G06F12/0862 ,  G06F12/0891 ,  G06F13/00 ,  G06F13/28

CPC classification number: G06F12/0808 ,  G06F12/0862 ,  G06F12/0891 ,  G06F2212/1016 ,  G06F2212/602 ,  G06F2212/6022 ,  G06F2212/6028

Abstract: An apparatus and method are described for a triggered prefetch operation. For example, one embodiment of a processor comprises: a first core comprising a first cache to store a first set of cache lines; a second core comprising a second cache to store a second set of cache lines; a cache management circuit to maintain coherency between one or more cache lines in the first cache and the second cache, the cache management circuit to allocate a lock on a first cache line to the first cache; a prefetch circuit comprising a prefetch request buffer to store a plurality of prefetch request entries including a first prefetch request entry associated with the first cache line, the prefetch circuit to cause the first cache line to be prefetched to the second cache in response to an invalidate command detected for the first cache line.